Self-aligned polysilicon emitter and contact structure for high performance bipolar transistors

Claim 2

A high performance bipolar device comprising a substrate including an epi-layer having a surface subject to processing steps in fabricating the device, a collector region, an intrinsic and extrinsic base region, both regions disposed in the epi-layer beneath the surface, a linking connection in the layer being disposed between the extrinsic and intrinsic base regions, an emitter region disposed in the intrinsic base region, and the surface overlying the linking connection and the emitter not exposed to deleterious etching during the formation of the intrinsic and extrinsic base and emitter regions whereby the device performance is improved due to the absence of defects at the surface which impair the performance of the device.

Claim 3

The device of claim 1 wherein an insulating layer overlies and surrounds the emitter region and serves as a mask during the formation of the emitter and intrinsic base region, the mask facilitating the formation of thicknesses for such regions suitable for high performance devices.

Claim 4

A complimentary set of NPN and PNP devices in a common substrate comprising: an epi-layer on a substrate, the layer having a surface subject to processing steps in fabricating the devices, isolation regions disposed in the epi-layer to define first and second areas for the NPN and PNP devices, respectively, the NPN device including a collector region, intrinsic and extrinsic base regions connected together by a linking connection in the layer and an emitter region disposed within the intrinsic base, all regions being within the first defined area and beneath the surface of the layer, the PNP device including a collector region, a base region, an emitter region, and a contact disposed on the base, all regions and the contact being within the second defined area beneath the surface of the layer, and the surfaces of the emitter in the first area and the contact in the second area not exposed to deleterious process during the formation of the other regions of the respective devices whereby the performance of the NPN and PNP devices is enhanced.

Claim 5

A complimentary set of NPN and PNP devices in a common substrate comprising: an epi-layer on a substrate, the layer having a surface subject to processing steps in fabricating the devices, isolation regions disposed in the epi-layer to define first and second areas for the NPN and PNP devices, respectively, the NPN device including a collector region, intrinsic and extrinsic base regions connected together by a linking connection in the layer and an emitter region disposed within the intrinsic base, all regions being within the first defined area and beneath the surface of the layer, the PNP device including a collector region, a base region, an emitter region, and a contact disposed on the base, all regions and the contact being within the second defined area beneath the surface of the layer, and the surfaces of the emitter in the first area and the contact in the second area not exposed to deleterious process during the formation of the other regions of the respective devices whereby the performance of the NPN and PNP devices is enhanced.

Claim 6

A process for forming a bipolar device having a self-aligned emitter region which includes a surface not subjected to deleterious processes during the formation of other active regions in the device comprising the steps of, forming an epi-layer on a substrate to be of a first conductivity type suitable as a collector region, forming and defining first and second overlying insulating layers of different materials at a selected point on the epi-layer for a future emitter region of the device, forming and controlling a linking region of a second conductivity type in the epi-layer to be adjacent to the future emitter region, forming and defining an insulating layer of a third isolating material on the layer as a sidewall surrounding the first and second overlying layers, the sidewall serving as a mask for aligning subsequent and sequentially formed emitter and intrinsic base regions, depositing and planarizing a layer of a fourth insulating material to expose the second insulating layer overlying the future emitter region, implanting through the deposited and planarized fourth insulating material the second conductivity type to form an extrinsic base region therebeneath, the exposed second insulating layer serving as a mask to the second conductivity type, removing the exposed second insulating layer to expose the first insulating layer overlying the future emitter region, implanting into the exposed first insulating layer, the second conductivity type and heating the substrate to drive the second conductivity into the epi-layer to serve as an intrinsic base region which is connected to the extrinsic base region through the linking region, implanting the first conductivity type into the first exposed layer and heating the substrate to drive-in the first conductivity type to form an emitter region disposed within the intrinsic base region, and forming metal connections to the emitter, base and collector regions whereby the device has enhanced performance due to the absence of deleterious processes affecting the surface of the layer overlying the emitter and linking regions.

Claim 7

A process for forming a bipolar device having a self-aligned emitter region which includes a surface not subjected to deleterious processes during the formation of other active regions in the device comprising the steps of, forming an epi-layer on a substrate to be of a first conductivity type suitable as a collector region, forming and defining first and second overlying insulating layers of different materials at a selected point on the epi-layer for a future emitter region of the device, forming and controlling a linking region of a second conductivity type in the epi-layer to be adjacent to the future emitter region, forming and defining an insulating layer of a third isolating material on the layer as a sidewall surrounding the first and second overlying layers, the sidewall serving as a mask for aligning subsequent and sequentially formed emitter and intrinsic base regions, depositing and planarizing a layer of a fourth insulating material to expose the second insulating layer overlying the future emitter region, implanting through the deposited and planarized fourth insulating material the second conductivity type to form an extrinsic base region therebeneath, the exposed second insulating layer serving as a mask to the second conductivity type, removing the exposed second insulating layer to expose the first insulating layer overlying the future emitter region, implanting into the exposed first insulating layer, the second conductivity type and heating the substrate to drive the second conductivity into the epi-layer to serve as an intrinsic base region which is connected to the extrinsic base region through the linking region, implanting the first conductivity type into the first exposed layer and heating the substrate to drive-in the first conductivity type to form an emitter region disposed within the intrinsic base region, and forming metal connections to the emitter, base and collector regions whereby the device has enhanced performance due to the absence of deleterious processes affecting the surface of the layer overlying the emitter and linking regions.

Claim 8

The process of Claim 5 wherein a chemical-mechanical process planarizes the fourth insulating material and the first insulating layer serves as a polishing stop.

Claim 9

The process of Claim 5 wherein the metal is selected to form a schottky barrier diode contact.

Claim 10

The process of Claim 5 wherein the first insulating layer is undoped polysilicon, the second insulating layer is silicon nitride, the third insulating layer is silicon dioxide and the fourth insulating layer is in situ doped polysilicon.

Claim 11

The process of Claim 5 wherein the step of forming and defining a linking region includes the steps of forming a layer of thermal oxide and implanting therein the second conductivity type.

Claim 12

The process of Claim 5 wherein the steps of forming a sidewall including defining the sidewall to overly the linking region.

Claim 13

The process of Claim 5 wherein a second bipolar device of opposite conductivity type is formed in the substrate by first performing the following steps: forming a dielectric insulation region in the epi-layer of a first conductivity type to establish first and second regions therein, which are electrically and physically isolated from each other, forming a photoresist layer across the surface of the epi-layer, patterning the photoresist layer to implant a second conductivity type in the second regions of the epi-layer to convert the first conductivity type therein and establish a collector region for a second device, and reforming and patterning the photoresist layer to implant the first conductivity in the second region to serve as a base region for the second device.

Claim 14

The process of claim 10 wherein the emitter region is formed for the second device at the same time the extrinsic region is formed for the bipolar device.

Claim 15

The process of claim 11 wherein a base contact is formed for the second device at the same time the emitter region is formed for the bipolar device.

Claim 16

The process of claim 12 wherein the bipolar device is an NPN type and the second device is a PNP type.