Patent US3622490A successfully refreshed from Google Patents.
Patent EP0314219A1 successfully refreshed from Google Patents.
EP0314219A1
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Line synchronising circuit
Assignee: Koninklijke Philips NV
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Filing: 1988-10-06
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Granted: —
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Expires: 2008-10-06
Abstract
Abstract A line synchronising circuit in a picture display device comprises a phase discriminator, a loop filter and a line oscillator constituting a control loop for controlling the frequency and/or the phase of the oscillator signal. To reduce the phase error, which occurs after a phase jump in the incoming signal, and to reduce the time in which the error is visible, the loop filter has a first part for supplying a first control signal having a first response time and a second part for supplying a second control signal having a second response time which is shorter than the first response time, the two parts of the loop filter being coupled to the control input of the line oscillator, and means for coupling the two parts or the second part, respectively, of the loop filter to the output of the phase discriminator.
Inventors
- 👤 Henricus Johannes Heerkens
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 05:39
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12; H04N5/126
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
164 words
A circuit for the line synchronisation in a picture display device, comprising a line oscillator, a phase discriminator having an input for receiving a signal generated by the oscillator, an input for receiving an incoming line synchronising signal and an output, a loop filter for smoothing the signal at the output of the phase discriminator and for applying the obtained control signal to a control input of the line oscillator for controlling the frequency and/or the phase of the oscillator signal, characterized in that the loop filter has a first part for supplying a first control signal having a first response time and a second part for supplying a second control signal having a second response time which is shorter than the first response time, the two parts of the loop filter being coupled to the control input of the line oscillator,and means for coupling the two parts or the second part, respectively, of the loop filter to the output of the phase discriminator.
Claim 2
Dependent Claim
164 words
A circuit for the line synchronisation in a picture display device, comprising a line oscillator, a phase discriminator having an input for receiving a signal generated by the oscillator, an input for receiving an incoming line synchronising signal and an output, a loop filter for smoothing the signal at the output of the phase discriminator and for applying the obtained control signal to a control input of the line oscillator for controlling the frequency and/or the phase of the oscillator signal, characterized in that the loop filter has a first part for supplying a first control signal having a first response time and a second part for supplying a second control signal having a second response time which is shorter than the first response time, the two parts of the loop filter being coupled to the control input of the line oscillator,and means for coupling the two parts or the second part, respectively, of the loop filter to the output of the phase discriminator.
Claim 3
Dependent Claim
143 words
A line synchronising circuit as claimed in Claim 1, also comprising a keying signal generator coupled to the line oscillator for generating a pulsatory keying signal derived from the oscillator signal in the case of a phase difference measured by the phase discriminator, which difference is one or a predetermined number of successive times smaller than a predetermined value, the central instant of a keying pulse and the central instant of a line synchronising pulse substantially coinciding in the synchronous state of the control loop constituted by the phase discriminator, the loop filter and the oscillator, characterized in that the two parts of the loop filter are coupled to the output of the phase discriminator during the occurrence of the keying pulses and in that the second part of the filter is coupled to said output outside the occurrence of the keying pulses.
Claim 4
Dependent Claim
58 words
A line synchronising circuit as claimed in Claim 2, characterized in that a switch controlled by the keying pulses connects the two parts of the loop filter to the output of the phase discriminator during the occurrence of said pulses and connects the second part of the filter to said output outside the occurrence of the keying pulses.
Claim 5
Dependent Claim
37 words
A line synchronising circuit as claimed in Claim 3, characterized in that the first part of the loop filter includes a voltage source and the second part includes a resistor, the two parts being arranged in series.
Claim 6
Dependent Claim
45 words
A line synchronising circuit as claimed in Claim 4, characterized in that the voltage source is formed by means of a first capacitor, a second capacitor whose capacitance is many times smaller than the capacitance of the first capacitor being arranged parallel to the resistor.
Claim 7
Dependent Claim
74 words
A line synchronising circuit as claimed in Claim 3, characterized in that the first part of the loop filter includes an integrator arranged in series with the switch and the second part includes a storage element which is resettable before the occurrence of a keying pulse, an adder stage adding the information from the integrator and the information from the storage element for applying said information to the control input of the line oscillator.
Claim 8
Dependent Claim
40 words
A line synchronising circuit as claimed in Claim 6, characterized by a sampling circuit incorporated between the adder stage and the control input of the line oscillator, said circuit being operative each time after the occurrence of a keying pulse.
Claim 9
Dependent Claim
76 words
A line synchronising circuit as claimed in Claim 1, characterized in that the two parts of the loop filter are coupled to the output of the phase discriminator in the case of a value of the phase difference measured by the phase discriminator which is lower than a predetermined value, the second part of the loop filter being coupled to said output in the case of a value which is higher than the said, predetermined value.
Claim 10
Dependent Claim
113 words
A line synchronising circuit as claimed in Claim 8, characterized in that a storage element is coupled to the output of the phase discriminator, with which element an integrator is connected in series with a switch, an adder stage adding the information from the integrator and the information from the storage element for applying said information to the control input of the line oscillator via a sampling circuit which is operative after the occurrence of a line synchronising pulse, the switch being conducting in the case of a value of the phase difference measured by the phase discriminator which is lower than the said, predetermined value and being blocked in the opposite case.
References Cited (Backward Citations)
DE2409166B1
Cited
US4214260A
Cited
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