Patent EP0313857A2 successfully refreshed from Google Patents.
EP0313857A2
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Buffer memory control apparatus
Assignee: Hitachi Ltd
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Filing: 1988-09-30
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Granted: —
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Expires: 2008-09-30
Abstract
Abstract For address identification of a cache memory (4), a part of address bits of a logical address which are subject to address translation through a TLB (2) and a part of address bits of the logical address which are not subject to address translation are applied in combination to an address array (3′) of the cache memory (4). Synonym generation is detected (46) in response to buffer miss and synonym invalidation (65) is executed in the buffer address array.
Inventors
- 👤 Tsuyoshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 15:20
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
162 words
A buffer memory control apparatus using a logical address-to-physical address translating mechanism for identifying a buffer corresponding to a memory in a digital computer system, said apparatus comprising: a first buffer address array (3′) arranged to be accessed with a part ((2, 2), (2, 3)) of a logical address ((0, 1)-(2, 3)) which is to be subject to address translation and a part ((2, 4)-(3, 0)) of a logical address which is not to be subject to address translation; a second buffer address array (44, 53, 66) arranged to be accessed with the part ((2, 4)-(3, 0)) of the logical address which is not to be subject to address translation; amd a buffer (4) storing data and arranged to be accessed with the part ((2, 2), (2, 3)) of the logical address ((0, 1)-(2, 3)) which is to be subject to address translation and a part ((2, 4)-(3, 3)) of a logical address which is not to be subject to address translation.
Claim 2
Dependent Claim
162 words
A buffer memory control apparatus using a logical address-to-physical address translating mechanism for identifying a buffer corresponding to a memory in a digital computer system, said apparatus comprising: a first buffer address array (3′) arranged to be accessed with a part ((2, 2), (2, 3)) of a logical address ((0, 1)-(2, 3)) which is to be subject to address translation and a part ((2, 4)-(3, 0)) of a logical address which is not to be subject to address translation; a second buffer address array (44, 53, 66) arranged to be accessed with the part ((2, 4)-(3, 0)) of the logical address which is not to be subject to address translation; amd a buffer (4) storing data and arranged to be accessed with the part ((2, 2), (2, 3)) of the logical address ((0, 1)-(2, 3)) which is to be subject to address translation and a part ((2, 4)-(3, 3)) of a logical address which is not to be subject to address translation.
Claim 3
Dependent Claim
85 words
A buffer memory control apparatus according to Claim 1, further comprising: means (42, 47) for applying said first buffer address array with a logical address to acess said first buffer address array (3′); means (5, 8) responsive to an output of said first buffer address array (3′) to detect address hit in said buffer; and an accessing means (43, 49) connected to said address hit detecting means for making access to said second buffer address array when no address bit in said buffer is detected.
Claim 4
Dependent Claim
82 words
A buffer memory control apparatus according to Claim 2, further comprising: means (46, 55, 68) responsive to the output of said second buffer address array (44, 53, 66) to detect hit of synonym; and means (65) connected to said synonym hit detecting means for invalidating blocks in said first and second buffer address arrays in which the synonym is included, on the basis of row and group numbers of the blocks, when synonym hit is detected by said synonym hit detecting means.
References Cited (Backward Citations)
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