Patent EP0312764A2 successfully refreshed from Google Patents.
EP0312764A2
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EP
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A data processor having multiple execution units for processing plural classes of instructions in parallel
Assignee: International Business Machines Corp
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Filing: 1988-09-12
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Granted: —
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Expires: 2008-09-12
Abstract
Abstract A data processor is disclosed which enables the selective simultaneous or asynchronous execution of mutually independent instructions of different classes in parallel coupled execution units and which enables the sequential execution of mutually dependent instructions of different classes by delaying the execution of a dependent instruction in a second execution unit until the completion of execution of a precursor instruction in a first execution unit. The instructions are dispatched to respective ones of a plurality of parallel coupled execution units, in accordance with their instruction class.
Inventors
- 👤 Ramesh Kumar Karne
- 👤 Sastry Sarvamangala Vedula
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 21:58
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3873; G06F9/3836; G06F9/3885; G06F9/3889
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
365 words
In a data processing system including a plurality of execution units selectively coupled to a memory and to a plurality of registers, for processing a sequence of instructions which include an op code, a source location reference and a result location reference, the op code of each instruction being classified into one of a plurality of classes, means for executing each instruction in a corresponding one of said plurality of execution units according to the class of the op code thereof, comprising: an instruction dispatcher having an input coupled to receive said sequence of instructions and an output connected to each of said plurality of execution units, for identifying the class of an op code in an instruction in said sequence and dispatching the instruction to one of said plurality of execution units corresponding to the identified class; a control unit having an input connected to said instruction dispatcher and also having an input connected from and an output connected to each of said plurality of execution units; said control unit storing a result location associated with a first occurring instruction in said sequence to be executed in a first one of said plurality of execution units; said control unit comparing said result location of said first occurring instruction with a source location associated with a second occurring instruction in said sequence to be executed in a second one of said plurality of execution units; said control unit delaying the execution of said second instruction until the completion of execution of said first instruction, if said associated source location matches said associated result location indicating that the execution of said second instruction depends on the result produced by the execution of said first instruction; said control unit enabling executing said first instruction in said first one of said plurality of execution units asynchronously with the execution of said second instruction in said second one of said plurality of execution units, if said associated source location does not match said associated result location indicating that said second instruction is independent of said first instruction; whereby mutually dependent instructions of different classes can be executed sequentially and mutually independent instructions of different classes can be executed asynchronously.
Claim 2
Dependent Claim
365 words
In a data processing system including a plurality of execution units selectively coupled to a memory and to a plurality of registers, for processing a sequence of instructions which include an op code, a source location reference and a result location reference, the op code of each instruction being classified into one of a plurality of classes, means for executing each instruction in a corresponding one of said plurality of execution units according to the class of the op code thereof, comprising: an instruction dispatcher having an input coupled to receive said sequence of instructions and an output connected to each of said plurality of execution units, for identifying the class of an op code in an instruction in said sequence and dispatching the instruction to one of said plurality of execution units corresponding to the identified class; a control unit having an input connected to said instruction dispatcher and also having an input connected from and an output connected to each of said plurality of execution units; said control unit storing a result location associated with a first occurring instruction in said sequence to be executed in a first one of said plurality of execution units; said control unit comparing said result location of said first occurring instruction with a source location associated with a second occurring instruction in said sequence to be executed in a second one of said plurality of execution units; said control unit delaying the execution of said second instruction until the completion of execution of said first instruction, if said associated source location matches said associated result location indicating that the execution of said second instruction depends on the result produced by the execution of said first instruction; said control unit enabling executing said first instruction in said first one of said plurality of execution units asynchronously with the execution of said second instruction in said second one of said plurality of execution units, if said associated source location does not match said associated result location indicating that said second instruction is independent of said first instruction; whereby mutually dependent instructions of different classes can be executed sequentially and mutually independent instructions of different classes can be executed asynchronously.
Claim 3
Dependent Claim
44 words
The system of claim 1, wherein said instruction dispatcher accesses a storage means containing an instruction map relating each of said op codes with a corresponding associated source location and associated result location which are output by said instruction dispatcher to said control unit.
Claim 4
Dependent Claim
36 words
The system of claim 1, wherein each of said classes of op codes in said plurality of classes represents functions which can only be executed in a respective, corresponding one of said plurality of execution units.
Claim 5
Dependent Claim
32 words
The system of claim 3, wherein said plurality of classes of op codes includes loading said registers, accessing said memory, executing fixed point arithmetic, executing floating point arithmetic, and performing branching operations.
References Cited (Backward Citations)
No citation records indexed.
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