Patent EP0312239A2 successfully refreshed from Google Patents.
EP0312239A2
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EP
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Message fifo buffer controller
Assignee: Nortel Networks Ltd
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Filing: 1988-10-05
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Granted: —
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Expires: 2008-10-05
Abstract
Abstract A FIFO (first in first out) control circuit (211) for providing address information to a FIFO memory (212). Two up counters (217, 218) are used; one to provide the write address and one to provide the read address. A multiplexer (219) selects which addresses (read or write) are used. Two storage registers (243,244) are used to temporarily "hold" the output from the counters. This enables the counters to be re-loaded with their original "count" to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Logic circuitry is used to provide two status output signals, name full (or not) and empty (or not).
Inventors
- 👤 Martin Claude Lefebvre
- 👤 Carmine Antonio Ciancibello
- 👤 Youssef Alfred Geadah
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 15:07
CPC Classifications
G; G11; G11C; G11C7/00; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F5/12; G06F5/14; G06F2205/00; G06F2205/06; G06F2205/062
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
149 words
A control circuit (211) for a FIFO (first in first out) memory circuit (210) for providing address information to a FIFO memory means (212), said control circuit comprising: a first means (217) for providing a first binary signal (223); a second means (218) for providing a second binary signal (222); a first storage means (243) for selectively receiving and storing the output of said first means; second storage means (244) for selectively receiving and storing the output of said second means (218); first comparator means (241) for comparing the output of said first storage means (243) with the output of said second means (218) and producing a first control signal (246) indicative of said comparison; and second comparator means (242) for comparing the output of said second storage means (244) with the output of said first means (217) and producing a second control signal (247) indicative of said comparison.
Claim 2
Dependent Claim
149 words
A control circuit (211) for a FIFO (first in first out) memory circuit (210) for providing address information to a FIFO memory means (212), said control circuit comprising: a first means (217) for providing a first binary signal (223); a second means (218) for providing a second binary signal (222); a first storage means (243) for selectively receiving and storing the output of said first means; second storage means (244) for selectively receiving and storing the output of said second means (218); first comparator means (241) for comparing the output of said first storage means (243) with the output of said second means (218) and producing a first control signal (246) indicative of said comparison; and second comparator means (242) for comparing the output of said second storage means (244) with the output of said first means (217) and producing a second control signal (247) indicative of said comparison.
Claim 3
Dependent Claim
23 words
The control circuit of claim 1 wherein said first means is a counter means and wherein said second means is a counter means.
Claim 4
Dependent Claim
52 words
The control circuit of claim 2 further including a multiplexer means (219) for receiving both said first signal and said second signal and selecting either said first or said second signal as its output whereby the output of said multiplexer, less the most significant bit, is used to address said FIFO memory.
Claim 5
Dependent Claim
127 words
The control circuit of claim 1, 2 or 3 wherein said second comparator comprises: third comparator means (248) for comparing the most significant bit of said first signal (223) with the most significant bit of the output from said second storage means (244) and producing a third control signal (249) indicative of said comparison; fourth comparator means (251) for comparing the bits of said first signal (223), less the most significant bit, with the bits from said second storage means (244), less the most significant bit, and producing a fourth control signal (252) indicative of said comparison; logic means (253), responsive to said third control signal and said fourth control signal, to produce said second control signal (247) indicative of said memory circuit being full or not.
Claim 6
Dependent Claim
191 words
A control circuit (211) for a FIFO (first in first out) memory circuit (210) for providing address information to a FIFO memory means (212), said control circuit comprising: first counter means (217) for providing a first signal (223); second counter means (218) for providing a second signal (222); multiplexer means (219) for receiving both said first signal and said second signal and selecting either said first or second signal as its output; first storage means (243) for selectively receiving and storing the output of said first counter means; second storage means (244) for selectively receiving and storing the output of said second counter means; first comparator means (241) for comparing the output of said first storage means (243) with the output of said second counter means (218) and producing a first control signal (246) indicative of said comparison; and second comparator means (242) for comparing the output of said second storage means (244) with the output of said first counter means (217) and producing a second control signal (247) indicative of said comparison; whereby the output of said multiplexer, less the most significant bit, is used to address said FIFO memory.
Claim 7
Dependent Claim
191 words
A control circuit (211) for a FIFO (first in first out) memory circuit (210) for providing address information to a FIFO memory means (212), said control circuit comprising: first counter means (217) for providing a first signal (223); second counter means (218) for providing a second signal (222); multiplexer means (219) for receiving both said first signal and said second signal and selecting either said first or second signal as its output; first storage means (243) for selectively receiving and storing the output of said first counter means; second storage means (244) for selectively receiving and storing the output of said second counter means; first comparator means (241) for comparing the output of said first storage means (243) with the output of said second counter means (218) and producing a first control signal (246) indicative of said comparison; and second comparator means (242) for comparing the output of said second storage means (244) with the output of said first counter means (217) and producing a second control signal (247) indicative of said comparison; whereby the output of said multiplexer, less the most significant bit, is used to address said FIFO memory.
Claim 8
Dependent Claim
27 words
The control circuit of claim 5 wherein said first storage means is a binary storage register and wherein said second storage means is a binary storage register.
Claim 9
Dependent Claim
124 words
The control circuit of claim 5 wherein said second comparator comprises: third comparator means (248) for comparing the most significant bit of said first signal (223) with the most significant bit of the output from said second storage means (244) and producing a third control signal (249) indicative of said comparison; fourth comparator means (251) for comparing the bits of said first signal, less the most significant bit, with the bits from said second storage means (244), less the most significant bit, and producing a fourth control signal (252) indicative of said comparison; and logic means (253), responsive to said third control signal and said fourth control signal, to produce said second control signal (247) indicative of said memory circuit being full or not.
Claim 10
Dependent Claim
14 words
The control circuit of claim 7 wherein said logic means is an AND gate.
Claim 11
Dependent Claim
229 words
A control circuit (211) for a FIFO (first in first out) memory circuit (210) for providing address information to a FIFO memory means (212), said control circuit comprising: first counter means (217) for providing a first binary signal (223); second counter means (218) for providing a second binary signal (222); multiplexer means (219) for receiving both said first signal and said second signal and selecting either said first or second signal as its output; first storage means (243) for selectively receiving and storing the output of said first counter means; second storage means (244) for selectively receiving and storing the output of said second counter means; first bus means (262) for applying the output of said first storage means to said first counter means; second bus means (261) for applying the output of said second storage means to said second counter means; first comparator means (241) for comparing the output of said first storage means (243) with the output of said second counter means (218) and producing a first control signal (246) indicative of said comparison; and second comparator means (242) for comparing the output of said second storage means (244) with the output of said first counter means (217) and producing a second control signal (247) indicative of said comparison; whereby the output of said multiplexer, less the most significant bit, is used to address said FIFO memory.
Claim 12
Dependent Claim
229 words
A control circuit (211) for a FIFO (first in first out) memory circuit (210) for providing address information to a FIFO memory means (212), said control circuit comprising: first counter means (217) for providing a first binary signal (223); second counter means (218) for providing a second binary signal (222); multiplexer means (219) for receiving both said first signal and said second signal and selecting either said first or second signal as its output; first storage means (243) for selectively receiving and storing the output of said first counter means; second storage means (244) for selectively receiving and storing the output of said second counter means; first bus means (262) for applying the output of said first storage means to said first counter means; second bus means (261) for applying the output of said second storage means to said second counter means; first comparator means (241) for comparing the output of said first storage means (243) with the output of said second counter means (218) and producing a first control signal (246) indicative of said comparison; and second comparator means (242) for comparing the output of said second storage means (244) with the output of said first counter means (217) and producing a second control signal (247) indicative of said comparison; whereby the output of said multiplexer, less the most significant bit, is used to address said FIFO memory.
Claim 13
Dependent Claim
27 words
The control circuit of claim 9 wherein said first storage means is a binary storage register and wherein said second storage means is a binary storage register.
Claim 14
Dependent Claim
124 words
The control circuit of claim 10 wherein said second comparator comprises: third comparator means (248) for comparing the most significant bit of the said first signal (223) with the most significant bit of output from said second storage means (244) and producing a third control signal (249) indicative of said comparison; fourth comparator means (251) for comparing the bits of said first signal, less the most significant bit, with the bits from said second storage means (244), less the most significant bit, and producing a fourth control signal (252) indicative of said comparison; and logic means (253), responsive to said third control signal and said fourth control signal, to produce said second control signal (247) indicative of said memory circuit being full or not.
Claim 15
Dependent Claim
14 words
The control circuit of claim 11 wherein said logic means is an AND gate.
References Cited (Backward Citations)
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