Patent US1333878A successfully refreshed from Google Patents.
Patent EP0311798A2 successfully refreshed from Google Patents.
EP0311798A2
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Data input/output circuit
Assignee: Sanyo Electric Co Ltd
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Filing: 1988-09-14
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Granted: —
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Expires: 2008-09-14
Abstract
Abstract A data input/output circuit includes a 32-bit reversible shift register (1) which includes four 8-bit reversible shift registers (2-5). Input gate circuits (6, 7) selectively apply data being inputted in a bit-serial fashion from an external to the 8-bit reversible shift registers (3, 4), and output gate circuits (8-12) selectively output data being stored in arbitrary stages of the 32-bit reversible shift register (1) in a bit-serial fashion. Input latches (13-15) and output latches (16-18) each of which is an 8-bit latch are connected to the respective 8-bit reversible shift registers (2-4) and a data bus (19). The input latches (13-15) hold the data being stored in the 8-bit reversible shift registers (2-4) and send the same onto the data bus (19) in a bit-parallel fashion, and the output latches (16-18) hold the data being sent from the data bus (19) and preset the same into the 8-bit reversible shift registers (2-4) in a bit-parallel fashion.
Inventors
- 👤 Mituyoshi Fukuda
- 👤 Masahisa Shimizu
- 👤 Hideki Ohashi
- 👤 Masaki Kawaguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 13:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/768; H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A data input/output circuit, comprising: an N-bit shift register (1) into which data can be preset; input gate means (6, 7) for selectively applying data being inputted from an external in a bit-serial fashion to an input of an arbitrary stage of the shift register; output gate means (8 - 12) for selectively output data of an arbitrary stage of the shift register in a bit-serial fashion; and control means (20) which generates a control signal (IG1, IG2, OG1-OG5) in accordance with a format of data to be processed so as to control the input gate means and the output gate means.
Claim 2
Dependent Claim
102 words
A data input/output circuit, comprising: an N-bit shift register (1) into which data can be preset; input gate means (6, 7) for selectively applying data being inputted from an external in a bit-serial fashion to an input of an arbitrary stage of the shift register; output gate means (8 - 12) for selectively output data of an arbitrary stage of the shift register in a bit-serial fashion; and control means (20) which generates a control signal (IG1, IG2, OG1-OG5) in accordance with a format of data to be processed so as to control the input gate means and the output gate means.
Claim 3
Dependent Claim
47 words
A data input/output circuit in accordance with claim 1, wherein said N-bit shift register includes a plurality (n) of K-bit (N = nK) shift registers (2 - 5) which are connected to each other so as to form said N-bit shift register as a cyclic shift register.
Claim 4
Dependent Claim
92 words
A data input/output circuit in accordance with claim 1 or 2, further comprising input latch means (13 - 15) connected to outputs of arbitrary M bits (M ≦ N) of the shift register for holding data being stored in the shift register for sending the same to a data bus (19) in a bit-parallel fashion; and output latch means (16 - 18) connected to preset terminals of the arbitrary M bits of the shift register to preset data being received from the data bus into the shift register in a bit-parallel fashion.
Claim 5
Dependent Claim
48 words
A data input/output circuit in accordance with any of the claims 1, 2 or 3, wherein said N-bit shift register is a reversible shift register and that said control means (20) further generates a control signal (U/D) in accordance with a shift direction of the reversible shift register.
Claim 6
Dependent Claim
24 words
A data input/output circuit in accordance with claim 4, wherein said plurality (n) of K-bit shift registers (2 - 5) are reversible shift registers.
Claim 7
Dependent Claim
77 words
A data input/output circuit in accordance with claim 5, wherein each of said plurality of K-bit reversible shift registers includes a first input (SUI) to which data is inputted in a bit-serial fashion when the data is to be shifted upward, a second input (SDI) to which data is inputted in a bit-serial fashion when the data is to be shifted downward, and a plurality of inputs/outputs (D-D7) to or from which data is inputted or outputted.
Claim 8
Dependent Claim
50 words
A data input/output circuit in accordance with any of the preceding claims, wherein said input latch means (13 - 15) and output latch means (16 - 18) are connected between said plurality of inputs/outputs of at least one of said plurality of K-bit (reversible) shift registers and said data bus.
Claim 9
Dependent Claim
74 words
A data input/output circuit in accordance with claim 6 or 7, wherein said input gate means includes a couple of gate circuits (6, 7) one of which being connected to said first input (SUI) of any one of said plurality of K-bit reversible shift registers (2 - 5) and the other of which being connected to said second input (SDI) of any one of said plurality of K-bit reversible shift registers (2 - 5).
Claim 10
Dependent Claim
49 words
A data input/output circuit in accordance with any of the preceding claims, wherein said output gate means include a plurality of gate circuits (8 - 12) selectively connected to one or more of said plurality of inputs/outputs of one or more of said plurality of K-bit reversible shift registers.
References Cited (Backward Citations)
No citation records indexed.
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