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EP0311046A2
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Programmable logic array circuit
Assignee: Fujitsu VLSI Ltd
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Filing: 1988-10-05
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Granted: —
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Expires: 2008-10-05
Abstract
Abstract A programmable logic array circuit includes a pulse signal generating circuit (70) for generating a pulse signal (ITD, ITD) by detecting a change in levels of input signals (E0 - En). A first transistor (Q2) for precharging a product term line (L1) is provided. A second transistor (Q4) is provided for discharging an OR array input line (L2). A third transistor (Q11) is provided for precharging an OR array output line (L3). The first through third transistors (Q2, Q4, Q11) are controlled by the pulse signal (ITD, ITD). In other words, the first through third transistors (Q2, Q4, Q11) are controlled in response to the signal change of the input signals (E0 - En). In order to facilitate the discharging operation with respect to the OR array input line (L2), a fourth transistor (Q7) may be provided on a side opposite to the second transistor (Q4).
Inventors
- 👤 Kiyoshi Itano
- 👤 Kohji Shimbayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
260 words
A programmable logic array circuit comprising an AND array (50) comprising a plurality of memory cells (51) connected to input lines and product term lines (L1), input signals (E0 - En) being supplied to the AND array through the input lines; an OR array (60) comprising a plurality of memory cells (61) connected to OR array input lines (L2) and OR array output lines (L3), output signals being extracted through the OR array output lines; and product term sensing buffer means (80) for sensing levels of the product term lines (L1), sensed levels being sent to the OR array (60) through the OR array input lines (L2), characterized in that the programmable logic array circuit comprises pulse signal generating means (70) for generating a pulse signal (ITD, ITD ) by detecting a change in levels of the input signals (E0 - En), and in that the product term sensing buffer (80) comprises first precharging means (Q2) for charging the product term lines (L1) up to a predetermined potential (V DD ) in response to the pulse signal ( ITD ) derived from the pulse signal generating means (70), and discharging means (Q4) for discharging the OR array input lines (L2) in response to the pulse signal (ITD) derived from the pulse signal generating means (70), and in that the programmable logic array circuit further comprises second precharging means (Q11) for charging the OR array input lines (L2) up to a predetermined potential (V DD ) in response to the pulse signal (ITD) derived from the pulse signal generating means (70).
Claim 2
Dependent Claim
260 words
A programmable logic array circuit comprising an AND array (50) comprising a plurality of memory cells (51) connected to input lines and product term lines (L1), input signals (E0 - En) being supplied to the AND array through the input lines; an OR array (60) comprising a plurality of memory cells (61) connected to OR array input lines (L2) and OR array output lines (L3), output signals being extracted through the OR array output lines; and product term sensing buffer means (80) for sensing levels of the product term lines (L1), sensed levels being sent to the OR array (60) through the OR array input lines (L2), characterized in that the programmable logic array circuit comprises pulse signal generating means (70) for generating a pulse signal (ITD, ITD ) by detecting a change in levels of the input signals (E0 - En), and in that the product term sensing buffer (80) comprises first precharging means (Q2) for charging the product term lines (L1) up to a predetermined potential (V DD ) in response to the pulse signal ( ITD ) derived from the pulse signal generating means (70), and discharging means (Q4) for discharging the OR array input lines (L2) in response to the pulse signal (ITD) derived from the pulse signal generating means (70), and in that the programmable logic array circuit further comprises second precharging means (Q11) for charging the OR array input lines (L2) up to a predetermined potential (V DD ) in response to the pulse signal (ITD) derived from the pulse signal generating means (70).
Claim 3
Dependent Claim
47 words
A programmable logic array circuit as claimed in claim 1, characterized in that the programmable logic array circuit further comprises second discharging means (Q7) for discharging the OR array input lines (L2) in response to the pulse signal (ITD) derived from the pulse signal generating means (70).
Claim 4
Dependent Claim
76 words
A programmable logic array circuit as claimed in claim 2, characterized in that each of the first and second precharging means (Q2, Q11) comprises a metal oxide semiconductor (MOS) transistor, in that each of the first and second discharging means (Q4, Q7) comprises a MOS transistor, and in that gates of the MOS transistors of the first and second precharging and discharging means (Q2, Q4, Q7, Q11) are supplied with the pulse signal (ITD, ITD ).
Claim 5
Dependent Claim
108 words
A programmable logic array circuit as claimed in any of claims 2 and 3, characterized in that the pulse signal generating means (70) generates the pulse signal which consists of a first pulse signal ( ITD ) and a second pulse signal (ITD), and in that the first pulse signal ( ITD ) is a low-active signal, and in that the second pulse signal corresponds to a pulse signal obtained by inverting the first pulse signal, and in that either one of the first and second pulse signals (ITD, ITD ) is supplied to each of the first and second precharging and discharging means (Q2, Q4, Q7, Q11).
Claim 6
Dependent Claim
94 words
A programmable logic array circuit as claimed in claim 4, characterized in that the first precharging means (Q2) comprises an n-channel MOS transistor provided for each of the product term lines (L1), and the first discharging means (Q4) comprises a p-channel MOS transistor provided for each of the OR array input lines (L2), and in that the first pulse signal ( ITD ) is supplied to the gate of the n-channel MOS transistor of the first precharging means (Q2) and to the gate of the p-channel MOS transistor of the first discharging means (Q4).
Claim 7
Dependent Claim
85 words
A programmable logic array circuit as claimed in any of claims 4 and 5, characterized in that the second precharging means (Q11) comprises an n-channel MOS transistor provided for each of the OR array output lines (L3), and the second discharging means (Q7) comprises an n-channel MOS transistor provided for each of the OR array input lines (L2), and in that the second pulse signal (ITD) is supplied to the gates of the n-channel MOS transistors of the second precharging and discharging means (Q11, Q7).
Claim 8
Dependent Claim
55 words
A programmable logic array circuit as claimed in any of claims 2 to 6, characterized in that the second discharging means (Q7) is located at an end of the OR array input lines (L2) opposite to end in that the product term sensing buffer means (80) is connected to the OR array input lines (L2).
Claim 9
Dependent Claim
107 words
A programmable logic array circuit as claimed in anyone of claims 4 to 7, characterized in that the pulse signal generating means (70) comprises detecting means (71) provided for each of the input signals (E0 - En) for detecting a change in levels of the input signals; an OR circuit (72) for receiving all the output signals of the detecting means (71), an output signal of the OR circuit (72) being the second pulse signal (ITD); and an inverter circuit (73) for inverting the output signal of the OR circuit (72), an output signal of the OR circuit (73) being the first pulse signal ( ITD ).
Claim 10
Dependent Claim
64 words
A programmable logic array circuit as claimed in anyone of claims 1 to 8, characterized in that the programmable logic array circuit further comprises a first pull-up means (Q3) for pulling the product term lines (L1) to the predetermined potential (V DD ), and a second pull-up means (Q10) for pulling the OR array output lines (L3) to the predetermined potential (V DD ).
Claim 11
Dependent Claim
170 words
A programmable logic array circuit as claimed in claim 8 or 9, characterized in that the detecting means (71) comprises first and second inverter circuits (INV1, INV2) which are cascade-connected; third and fourth inverter circuits (INV3, INV4) each being connected to an output terminal of the second inverter circuit (INV2); fifth inverter circuit (INV5) being connected to an output terminal of the third inverter circuit (INV3); and first and second MOS transistors (Q13, Q14) for controlling the fourth and fifth inverter circuits (INV4, INV5), respectively, and in that a gate of the first MOS transistor (Q14) is connected to an output terminal of the fifth inverter circuit (INV5), and a gate of the second MOS transistor (Q14) is connected to an output of the fourth inverter circuit (INV4), and in that the detecting means (70) further comprises an NAND circuit (74) connected to the output terminals of the fourth and fifth inverter circuits (INV4, INV5); and an inverter circuit (75) connected to an output terminal of the NAND circuit (74).
Claim 12
Dependent Claim
142 words
A programmable logic array circuit as claimed in claim 2 or 3, characterized in that the pulse signal generating means (170) generates the pulse signal which consists of first, second, third and fourth pulse signals ( ITD1 , ITD2 , ITD3, ITD4), and in that the first and second pulse signals ( ITD1 , ITD2 ) are low-active signals, and in that a trailing edge of each of the second, third and fourth pulse signals ( ITD2 , ITD3, ITD4) lags behind a trailing edge of the first pulse signal ( ITD1 ), and in that the first and second pulse signals ( ITD1 , ITD2 ) are supplied to the first precharging and discharging means (Q2, Q4), respectively, and in that the third and fourth pulse signals (ITD3, ITD4) are supplied to the second discharging and precharging means (Q7, Q11), respectively.
Claim 13
Dependent Claim
140 words
A programmable logic array circuit as claimed in claim 11, characterized in that the pulse signal generating means comprises detecting means (71) provided for each of the input signals (E0 - En) for detecting a change in levels of the input signals; a NOR circuit (75) for receiving all the output signals of the detecting means (71), an output signal of the NOR circuit (75) being the first pulse signal ( ITD1 ); a first inverter circuit (77) for inverting the output signal of the NOR circuit (75), an output signal of the first inverter circuit (77) being the third and fourth pulse signals (ITD3, ITD4); and a second inverter circuit (79) for inverting the output signal of the first inverter circuit (77), an output signal of the second inverter circuit (79) being the second pulse signal ( ITD2 ).
Claim 14
Dependent Claim
74 words
A programmable logic array circuit as claimed in claim 12, characterized in that the pulse signal generating means (170) comprises a buffer circuit composed of two cascaded inverters (76, 78), and in that first pulse signal (ITD1) derived from the NOR circuit (75) is supplied to an input of the buffer circuit, so that an output signal of the buffer circuit is supplied to the first precharging means (Q2) as the first pulse signal
References Cited (Backward Citations)
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