Patent EP0311034B1 successfully refreshed from Google Patents.
EP0311034B1
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EP
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Cache memory control apparatus for a virtual memory data-processing system
Assignee: Hitachi Ltd
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Filing: 1988-10-05
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Granted: 1994-03-16
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Expires: 2008-10-05
Abstract
No abstract record available.
Inventors
- 👤 Atsushi Tanaka
- 👤 Tsuyoshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 20:10
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
298 words
A buffer memory control apparatus comprising: a buffer memory (81) for storing a part of information stored in a main storage; a buffer address array (BAA) storing respective main storage real addresses of data blocks stored in said buffer memory; an address translation mechanism (TLB) for translating a logical address into a real address when a memory access request at said logical address is made, said address translation mechanism being functionally divisible into a directory of logical address entries (TLBLA) and a directory of real address entries (TLBRA); comparator means (63, 73) for detecting coincidence between the real addresses produced by said address translation mechanism and the corresponding real addresses produced by said buffer address array; said logical address having a translatable portion (bits 1-19) actually supplied to said address translation mechanism, and another portion (bits 18-28) for directly addressing said buffer memory, said two portions of the logical address having a plurality of overlapping bits (bits 18, 19); said buffer memory control apparatus being characterized in that the logical address directory (TLBLA) and the real address directory (TLBRA) of said address translation mechanism are implemented on separate integrated circuits; said real address directory (TLBRA) and said buffer address array (BAA) are further divided into a plurality of real address storage portions (61, 71) and of buffer address sub-arrays (62, 72), respectively, whereby a correspondence is established between those real address storage portions and those buffer address sub-arrays being selected by the same state of at least one (bit 19) of said plurality of overlapping bits; corresponding ones (61, 62; 71, 72) of said real address storage portions and of said buffer address sub-arrays are implemented on the same integrated circuit (60; 70) together with the comparator means (63; 73) for detecting coincidence between the corresponding real addresses.
Claim 2
Dependent Claim
34 words
A buffer memory control apparatus according to claim 1, further comprising selecting means (64, 74, 80, 82) connected to an output of said comparator means for selecting storage data of said buffer memory (81).
Claim 3
Dependent Claim
89 words
A buffer memory control apparatus according to claim 2, in which said address translation mechanism includes a plurality of logical address directory portions (TLBLA, 51), and in which said buffer memory control apparatus further comprises a second comparator means (52, 53) for comparing an output of each of said plurality of logical address directory portions (TLBLA, 51) with a logical address, an output of said second comparator means being supplied to said selecting means (64, 74, 80, 82) so as to be used to perform the storage data selection.
References Cited (Backward Citations)
No citation records indexed.
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