EP0309330A2 — Access priority control system for main storage f…

Claim 1

Independent Claim 151 words

An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage, said system comprising: first access request port means for holding at least temporarily a segment address of the storage access requests from the processor; first control means responsive to the output of said first access request port means for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; second access request port means responsive to the output of said first control means for holding at least temporarily an intra-segment address of said storage access request; and second control means responsive to the output of said second access request port means for checking logical storage busy conditions in the storage segments.

Claim 2

Dependent Claim 151 words

An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage, said system comprising: first access request port means for holding at least temporarily a segment address of the storage access requests from the processor; first control means responsive to the output of said first access request port means for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; second access request port means responsive to the output of said first control means for holding at least temporarily an intra-segment address of said storage access request; and second control means responsive to the output of said second access request port means for checking logical storage busy conditions in the storage segments.

Claim 3

Dependent Claim 34 words

A system according to claim 1, wherein the checking of the bus conflict condition and the prohibition condition and the checking of the logical storage busy condition are carried out in different clock cycles.

Claim 4

Dependent Claim 33 words

A system according to claim 1, wherein said first control means comprises a comparator circuit for comparing the segment address of the storage access request with the segment address indicating a bus-in-use state.

Claim 5

Dependent Claim 42 words

A system according to claim 1, wherein said second control means is a busy check circuit for decoding the intra-segment address of the storage access request and checking the coincidence between the decoded signal and a busy signal for the storage banks.

Claim 6

Dependent Claim 27 words

A system according to claim 1, wherein a cycle in which the checking by said first control means is carried out corresponds to a request transfer cycle.

Claim 7

Dependent Claim 114 words

An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage, said system comprising at least one access request bus between the processor and the main storage corresponding to a unit data length, an access request from the processor to the main storage being transmitted with the unit data length or a multiple of the unit data length, a block access from the processor to the main storage being divided into a plurality of smaller access units corresponding to the unit data length in the processor.

Claim 8

Dependent Claim 114 words

An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage, said system comprising at least one access request bus between the processor and the main storage corresponding to a unit data length, an access request from the processor to the main storage being transmitted with the unit data length or a multiple of the unit data length, a block access from the processor to the main storage being divided into a plurality of smaller access units corresponding to the unit data length in the processor.

Claim 9

Dependent Claim 32 words

A system according to claim 6, wherein an access request is transmitted to the main storage for each unit data length so that the transmitting orders of block accesses are optionally controlled.

Claim 10

Dependent Claim 112 words

A system according to claim 6, wherein said system comprises first priority cycle means for the processor for checking bus conflicts between access ports corresponding to segments of the main storage and second priority cycle means for the processor for checking logical storage busy conditions, a checking of conflicts between buses corresponding to the access ports being carried out by said first priority cycle means, a checking of busy conditions of logical storage banks for each bus being carried out by said second priority cycle means, an access request being transmitted to a logical storage bank for each unit data when the result of the busy condition checking indicates a non-busy state.

Claim 11

Dependent Claim 94 words

A system according to claim 6, wherein said system comprises priority acquisition control table means for controlling a priority acquisition for unit data from each access port in the second priority cycle, a completion of transmitting of all unit data of block constituted by a plurality of unit data from access ports being detected according to priority information for each unit data of said priority acquisition control table means, a completion of the block access being determined on the basis of the results of said detection of a completion of all unit data transmitting.

Claim 12

Dependent Claim 190 words

An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage, said system comprising at least one access request bus between the processor and the main storage corresponding to a unit data length, and at least one first request port, for an access request from the processor to the main storage, for setting an access request corresponding to an access request element which is an element having a unit data length or a length shorter than this unit data length, the order of the access request elements being designated with regard to the execution of a program of operation of the system, a selection of access bus according to address indication position of a request being carried out concerning the output signal of the first request port, non-occurrence of a reversal of the order designated for execution of the program of the system being ensured where a setting is carried out to a second access port corresponding to the access request bus.

Claim 13

Dependent Claim 190 words

An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage, said system comprising at least one access request bus between the processor and the main storage corresponding to a unit data length, and at least one first request port, for an access request from the processor to the main storage, for setting an access request corresponding to an access request element which is an element having a unit data length or a length shorter than this unit data length, the order of the access request elements being designated with regard to the execution of a program of operation of the system, a selection of access bus according to address indication position of a request being carried out concerning the output signal of the first request port, non-occurrence of a reversal of the order designated for execution of the program of the system being ensured where a setting is carried out to a second access port corresponding to the access request bus.

Claim 14

Dependent Claim 46 words

A system according to claim 10, wherein a checking of conflicts only in an access request bus in question is carried out for the output signal of the second request port, to determine whether or not a transmitting of an access request in question is approved.

Claim 15

Dependent Claim 175 words

A system according to claim 10, wherein said system comprises a first priority cycle means for setting access request in the second access port in the regular sequence in accordance with a result of a checking of bus conflicts between the first request ports corresponding to main storage segments and a pointer for designating an order in a program execution sequence, and a second priority cycle means for checking logical storage busy conditions for unit data in main storage segments, an access request being selected and set in the second access port by the first priority cycle means by giving the highest priority to the result of conflict checking between buses corresponding to the request ports and to the port designation by the pointer, a logical storage bank busy checking in a bus in question being carried out for each access port by the second priority cycle means, and, when the result of the logical storage bank busy checking indicates a non-busy state, a transmitting of access request for each unit data is carried out.

Access priority control system for main storage for computer

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