Process for self-aligning the floating gates of non-volatile memory floating gate transistors, and memory obtained by this process

Abstract

Abstract The floating gates of floating-gate transistors of a non-volatile memory are self-aligned by producing, on a silicon substrate (1), a gate oxide layer (2) overlaid successively with a polysilicon layer (3) which is subsequently lightly oxidised (13), and itself overlaid with a silicon nitride layer (4). Silicon nitride lands (5) are defined corresponding to the sites of the floating gates of the transistors. After definition and reactive plasma etching, a second finer nitride layer (14) is deposited. This second layer is then removed by full field plasma etching. It is shown that spacers (17, 18) are thereby left which protect the sides (15, 16) of the lands. A thick insulating oxide (6) is then grown between the lands. It is shown that the width edges of the conduction channels of the transistors are thereby simply aligned with the bird-beak ends of the thick oxide regions. <IMAGE>

Inventors

• 👤 Albert Bergemont

Bibliographic Details