Patent EP0307722A1 successfully refreshed from Google Patents.
EP0307722A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device having improved multilayered wirings
Assignee: Toshiba Corp
•
Filing: 1988-08-31
•
Granted: —
•
Expires: 2008-08-31
Abstract
Abstract A semiconductor device includes a circuit block (11) formed on a semiconductor chip with multilayered wiring layers having two or more layers, and having a specific function assigned thereto, a first current path pattern (12) formed in a first layer of the multilayered wiring layers and running around the circuit block (11), a second current path pattern (13) formed in a second layer of the multilayered wiring layers and running around the circuit block (11), part of the second current path pattern (13) lying over the first current path pattern (12) and the other portion of the second current path pattern (13) lying off the first current path pattern (12) so as to define a connection space with a predetermined width (X) between the first current path pattern (12) and the second current path pattern (13), a first signal path pattern (14A) formed in the first layer of the multilayered wiring layers and serving as a signal path to the circuit block (11), a second signal path pattern (14B) formed in the second layer of the multilayered wiring layers and serving as the signal path to the circuit block (11), and a via contact (15), formed in the connection space, for electrically coupling the first signal path pattern (14A) and the second signal path pattern (14B).
Inventors
- 👤 Motohiro C/O Patent Division Enkaku
- 👤 Toshiya Kato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 13:23
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W20/43; H10W70/62; H10W70/63; H10W70/635; H10W72/00; H10W72/90
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
219 words
A semiconductor device comprising: at least one circuit block (11) formed on a semiconductor chip with multilayered wiring layers having two or more layers, and having a specific function assigned thereto; a first current path pattern (12) formed in a first layer of said multilayered wiring layers and running around said circuit block (11); a second current path pattern (13) formed in a second layer of said multilayered wiring layers and running around said circuit block (11), part of said second current path pattern (13) lying over said first current path pattern (12) and the other portion of said second current path pattern (13) lying off said first current path pattern (12) so as to define a connection space with a predetermined width (X or Y) between said first current path pattern (12) and said second current path pattern (13); a first signal path pattern (14A) formed in said first layer of said multilayered wiring layers and serving as a signal path to said circuit block (11); a second signal path pattern (14B) formed in said second layer of said multilayered wiring layers and serving as said signal path to said circuit block (11); and connecting means (15), formed in said connection space, for electrically coupling said first signal path pattern (14A) and said second signal path pattern (14B).
Claim 2
Dependent Claim
219 words
A semiconductor device comprising: at least one circuit block (11) formed on a semiconductor chip with multilayered wiring layers having two or more layers, and having a specific function assigned thereto; a first current path pattern (12) formed in a first layer of said multilayered wiring layers and running around said circuit block (11); a second current path pattern (13) formed in a second layer of said multilayered wiring layers and running around said circuit block (11), part of said second current path pattern (13) lying over said first current path pattern (12) and the other portion of said second current path pattern (13) lying off said first current path pattern (12) so as to define a connection space with a predetermined width (X or Y) between said first current path pattern (12) and said second current path pattern (13); a first signal path pattern (14A) formed in said first layer of said multilayered wiring layers and serving as a signal path to said circuit block (11); a second signal path pattern (14B) formed in said second layer of said multilayered wiring layers and serving as said signal path to said circuit block (11); and connecting means (15), formed in said connection space, for electrically coupling said first signal path pattern (14A) and said second signal path pattern (14B).
Claim 3
Dependent Claim
53 words
The semiconductor device according to claim 1, characterized in that said first signal path pattern (14A) extends under said second current path pattern (13) to outward of said circuit block (11) and said second signal path pattern (14B) extends over said first current path pattern (12) to inward of said circuit block (11).
Claim 4
Dependent Claim
35 words
The semiconductor device according to claim 1 or 2, characterized in that said first current path pattern (12) and said second current path pattern (13) serve as power feeding paths to said circuit block (11).
Claim 5
Dependent Claim
76 words
The semiconductor device according to claim 3, characterized in that a direction of a source current flowing through said first current path pattern (12) is opposite to that of a source current flowing through said second current path pattern (13), whereby said source current of said first current path pattern (12) cancels a magnetic field generated by said source current of said second current path pattern (13), thereby reducing inductance components of said power feeding paths.
Claim 6
Dependent Claim
60 words
The semiconductor device according to claim 3, characterized in that high frequency components in said source currents on said power feeding paths are bypassed by capacitance components formed between said first current path pattern (12) and said second current path pattern (13) at those portions thereof at which said first and second current path patterns (12, 13) overlap each other.
Claim 7
Dependent Claim
39 words
The semiconductor device according to any one of claims 1 to 5, characterized in that said connecting means (15) includes a via contact for electrically coupling said first signal path pattern (14A) to said second signal path pattern (14B).
Claim 8
Dependent Claim
29 words
The semiconductor device according to any one of claims 1 to 6, characterized in that said first and second current path patterns (12, 13) contain a high conductive metal.
Claim 9
Dependent Claim
86 words
The semiconductor device according to any one of claims 1 to 7, characterized in that two or more circuit blocks (11C, 11D) assigned with respective predetermined functions are formed on said semiconductor chip and said first current path pattern (12) surrounding one (11C) of said circuit blocks (11C, 11D) is at least partially coupled in parallel to said first current path pattern (12) surrounding an other one (11D) of said circuit blocks (11C, 11D), thereby reducing an electric resistance of said first current path pattern (12).
Claim 10
Dependent Claim
83 words
The semiconductor device according to claim 1 or 8, characterized in that two or more circuit blocks (11C, 11D) assigned with respective predetermined functions are formed on said semiconductor chip and said second current path pattern (13) surrounding one (11C) of said circuit blocks (11C, 11D) is at least partially coupled in parallel to said second current path pattern (13) surrounding an other one (11D) of said circuit blocks (11C, 11D), thereby reducing an electric resistance of said second current path pattern (13).
References Cited (Backward Citations)
GB2137413A
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.