Patent EP0306305A2 successfully refreshed from Google Patents.
EP0306305A2
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Image processor with free flow pipeline bus
Assignee: 3M Co
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Filing: 1988-09-01
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Granted: —
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Expires: 2008-09-01
Abstract
Abstract A digital image processing system (10) has a pipeline bus (30) for transferring addresses and data in parallel among the components of the system, which include an image memory (16), an address generator (18) and an intensity processor (20). The pipeline bus (30) includes a pipeline address bus (34), a pipeline data bus (36), and a master timing bus (38). Through the use of handshake signals, the pipeline bus (30) permits a free flow of pipelined data among the components at whatever rate is necessary to complete the particular processing task. Image data is transferred in the form of N x N pixel subimage blocks which can be addressed using a single address.
Inventors
- 👤 Dwight E.- C/O Minnesota Mining And Brown
- 👤 Mark S. -C/O Minnesota Mining And Laughery
- 👤 Thomas A. Lang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 19:28
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
82 words
A digital image processing system comprising: pipeline bus means for transmitting addresses and data, and for transmitting handshake signals for controlling flow of addresses and data over the pipeline bus means; image memory means connected to the pipeline bus means for storing digital image data; address generator means connected to the pipeline bus means for generating the addresses; and processor means connected to the pipeline bus means for performing processing operations on the digital image data received over the pipeline bus means.
Claim 2
Dependent Claim
82 words
A digital image processing system comprising: pipeline bus means for transmitting addresses and data, and for transmitting handshake signals for controlling flow of addresses and data over the pipeline bus means; image memory means connected to the pipeline bus means for storing digital image data; address generator means connected to the pipeline bus means for generating the addresses; and processor means connected to the pipeline bus means for performing processing operations on the digital image data received over the pipeline bus means.
Claim 3
Dependent Claim
37 words
The digital image processing system of claim 1 wherein the pipeline bus means comprises: pipeline address (PA) bus means over which the addresses are transmitted; and pipeline data (PD) bus means over which the data is transmitted.
Claim 4
Dependent Claim
26 words
The digital image processing system of claim 2 wherein the pipeline bus means transmits digital image data in a format which represents a multipixel subimage block.
Claim 5
Dependent Claim
85 words
A digital image processing system comprising: image memory means for storing digital image data for a plurality of pixels; address generator means for addressing the image memory means by providing an address representing a predetermined pixel of a multipixel subimage block; processor means for receiving and processing pixel data for the subimage block; and pipeline bus means connected to the image memory means, the address means and the processor means for transmitting the addresses produced by the address generator means and data representing subimage blocks.
Claim 6
Dependent Claim
85 words
A digital image processing system comprising: image memory means for storing digital image data for a plurality of pixels; address generator means for addressing the image memory means by providing an address representing a predetermined pixel of a multipixel subimage block; processor means for receiving and processing pixel data for the subimage block; and pipeline bus means connected to the image memory means, the address means and the processor means for transmitting the addresses produced by the address generator means and data representing subimage blocks.
Claim 7
Dependent Claim
20 words
The digital image processing system of claim 3 or 4 wherein the subimage block is a rectangular block of pixels.
Claim 8
Dependent Claim
17 words
The digital image processing system of claim 5 wherein the pixels of the subimage block are contiguous.
Claim 9
Dependent Claim
21 words
The digital image processing system of claim 6 wherein the subimage block is an N x N block of contiguous pixels.
Claim 10
Dependent Claim
12 words
The digital image processing system of claim 7 wherein N = 4.
Claim 11
Dependent Claim
98 words
The digital image processing system comprising: pipeline bus means for transmitting addresses and data; image memory means connected to the pipeline bus means for storing digital image data; address generator means connected to the pipeline bus means for generating the addresses; processor means connected to the pipeline bus means for performing processing operations on the digital image data received over the pipeline bus means; video display means for displaying images based upon the video signals; and display formatter means connected to the pipeline bus means for asynchronously converting data from the pipeline bus means to the video signals.
Claim 12
Dependent Claim
98 words
The digital image processing system comprising: pipeline bus means for transmitting addresses and data; image memory means connected to the pipeline bus means for storing digital image data; address generator means connected to the pipeline bus means for generating the addresses; processor means connected to the pipeline bus means for performing processing operations on the digital image data received over the pipeline bus means; video display means for displaying images based upon the video signals; and display formatter means connected to the pipeline bus means for asynchronously converting data from the pipeline bus means to the video signals.
Claim 13
Dependent Claim
160 words
The digital image processing system of claim 9 wherein the display formatter means includes: first and second address converter means; and control means responsive to a system clock from the pipeline bus means and a video clock from the video display means, the control means during a first portion of each operating cycle of the display formatter writing digital image data from the pipeline bus means into the first address converter means at a rate controlled by the system clock while reading digital image data from the second address converter means at a rate controlled by the video clock to produce the video signals, and during a second portion of each operating cycle reading digital image data from the first address converter means at a rate controlled by the video clock to produce the video signals while writing digital image data from the pipeline bus means into the second address converter means at a rate controlled by the system clock.
References Cited (Backward Citations)
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