Drop/insert processing circuit

Claim 2

A drop/insert processing circuit for dropping low speed data from high speed data or inserting low speed data into high speed data, said high speed data having a frame consisting of a plurality of channels, each channel being synchronous with a high-frequency clock signal, and said drop/insert processing circuit comprising: a clock signal generating circuit (71) for dividing said high-frequency clock signal into a low-frequency clock signal; a shift register (72) for serially receiving and shifting high speed data in response to said high-frequency clock signal; low speed data insertion control means (73) for inserting, in response to said low-frequency clock signal and a data insertion control signal, low speed data into a channel, specified by said data insertion control signal, in said high speed data passing through said shift register; and low speed data dropping means (74) for dropping, in response to said low-frequency clock signal, low speed data from the shift register; said low-frequency clock signal having one enable period corresponding to one of said channels in the frame of said high speed data and being synchro­nous with at least one of the outputs of said low speed data dropping means; wherein, said clock signal generating circuit and said shift register are used in common by both said low speed data insertion control means and said low speed data dropping means.

Claim 3

A drop/insert processing circuit as claimed in claim 1, wherein; said shift register (72) comprises a plurality of first latching circuits (81-1, ..., 81-n, and 81-(n+1), for serially receiving and shifting high speed data in response to said high-frequency clock signal; said low speed data insertion control means (73) comprises a plurality of control circuits (83-1, 83-2, ... and 83-n) for passing said low-fre­quency control signal in response to said data insertion control signal, and a plurality of low speed data inserting switches (82-1, 82-2, ... and 82-n) each being connected to one of said control circuits and connected between two adjacent said first latching circuits, to selectively output either said high speed data and said low speed data in response to said low-frequency clock signal passed through said control circuit; and said low speed data dropping means (74) comprises a plurality of second latching circuits (84-1, 84-2, ... and 84-n), respectively connected to outputs of said first latching circuits, for incorporating and outputting the corresponding one of outputs of said first latching circuits (1-2 to 1-n} in response to said low-frequency clock signal, in order to drop low speed data.

Claim 4

A drop/insert processing circuit as claimed in claim 2, wherein each of said low speed data inserting switches comprises a first input terminal for receiving high speed data output from a pre-stage of the first latching circuit, a second input terminal for receiving one bit of parallel data of said low speed data, and an output terminal for selectively outputting either said high speed data and said low speed data in response to said low-frequency clock signal passed through the corresponding control circuit, whereby said low speed data is inserted to a channel specified by said control signal.

Claim 5

A drop/insert processing circuit as claimed in claim 1, wherein said high speed data has a bit rate of f bits/s and said high-frequency clock signal has a frequency f .

Claim 6

A drop/insert processing circuit as claimed in claim 4, wherein said low speed data has a bit rate of f bits/n and said low-frequency clock signal has a frequency of f/n.

Claim 7

A drop/insert processing circuit as claimed in claim 5, wherein said low-frequency clock signal has a duty ratio of 1:(n-1).

Claim 8

A drop/insert processing circuit as claimed in claim 6, wherein a number of said first latching cir­cuits in said shift register is (n+1) , and a number of said second latching circuits is n .

Claim 9

A drop/insert processing circuit as claimed in claim 7, wherein said second latching circuits respec­tively have input terminals for receiving outputs of said first latching circuits, except for a final stage of the first latching circuits.

Claim 10

A drop/insert processing circuit as claimed in claim 2, wherein each of said first latching circuits except for the final stage latching circuit has two output terminals for providing shifted high speed data, one of said output terminals being connected to said first input terminal of said low speed data inserting means, and the other of said output terminals being connected to said input of said corresponding second latching circuit.

Claim 11

A drop/insert processing circuit as claimed in claim 9, wherein the final stage of said first latching circuits has a single output for providing output high speed data.

Claim 12

A drop/insert processing circuit as claimed in claim 1, wherein said clock signal generating circuit comprises a frequency divider (941) for dividing an input high-frequency clock signal into a low-frequency clock signal, and a synchronization detecting circuit (942) for establishing a synchronization between said low-frequency clock signal and dropped low speed data.

Claim 13

A drop/insert processing circuit, comprising: a shift register (81) including (n+1) first latching circuits (81-1, 81-2, ... and 81-(n+1)), for shifting data of f bits/s in response to a clock signal having a frequency f; n data inserting circuits (82-1, 82-2, ... and 82-n) each being connected between two adjacent said first latching circuits; n second latching circuits (83-1, 83-2, ... and 83-n) , for incorporating in response to a second clock signal having a frequency of f/n and having a duty ratio of 1:(n-1), outputs of all of the latching cir­cuits (81-2 to 81-n) in said shift register up to the last stage latching circuit (81-1); a clock signal generating circuit (84) for dividing said first clock signal and for generating a second clock signal which is synchronous with the output of said second clock signal; and n data insertion selecting switches (85-1, 85-2, ... and 85-n) each having an end func­tioning as a control input and having another input for receiving said second clock signal to determine whether or not data should be inserted; said second clock signal being supplied through a corresponding one of said data insertion selecting switches, which is in the ON state, to the corresponding one of said data inserting circuit so that a bit corresponding to the data of f/n bits/s is inserted to the corresponding latching circuit, and; data of f/n /s is dropped from said second latching circuits.

Claim 14

A drop/insert processing circuit, comprising: a shift register (81) including (n+1) first latching circuits (81-1, 81-2, ... and 81-(n+1)), for shifting data of f bits/s in response to a clock signal having a frequency f; n data inserting circuits (82-1, 82-2, ... and 82-n) each being connected between two adjacent said first latching circuits; n second latching circuits (83-1, 83-2, ... and 83-n) , for incorporating in response to a second clock signal having a frequency of f/n and having a duty ratio of 1:(n-1), outputs of all of the latching cir­cuits (81-2 to 81-n) in said shift register up to the last stage latching circuit (81-1); a clock signal generating circuit (84) for dividing said first clock signal and for generating a second clock signal which is synchronous with the output of said second clock signal; and n data insertion selecting switches (85-1, 85-2, ... and 85-n) each having an end func­tioning as a control input and having another input for receiving said second clock signal to determine whether or not data should be inserted; said second clock signal being supplied through a corresponding one of said data insertion selecting switches, which is in the ON state, to the corresponding one of said data inserting circuit so that a bit corresponding to the data of f/n bits/s is inserted to the corresponding latching circuit, and; data of f/n /s is dropped from said second latching circuits.

Claim 15

A drop/insert processing circuit as claimed in claim 1, wherein; said shift register (72) comprises a plurality of first latching circuits (120-1, ..., 120-n, and 120-(n+1), for serially receiving and shifting high speed data in response to said high-frequency clock signal; said low speed data insertion control means (73) comprises a plurality of second latching circuits (121-1 to 121-8) for latching input low speed data in parallel in response to said low-frequency clock signal, a plurality of third latching circuits (122-1 to 122-8) for respectively latching outputs of said first latching circuits, a plurality of low speed data inserting switches (123-1, 123-2, ... and 123-n) each having a first input terminal connected to an output of the corresponding one of said second latching circuits, a second input terminal connected to an output of the corresponding one of said third latching circuits, and an output terminal for output­ting, in response to said data insertion control signal, either of the outputs of the corresponding one of said first or second latching circuits, and a multiplexing circuit (124) having a plurality of input terminals respectively connected to output terminals of said low speed data inserting switches, for multiplexing input data to obtain output high speed data; said low speed data dropping means (74) comprises said third latching circuits, the dropped signal being obtained at output terminals thereof.

Claim 16

A drop/insert processing circuit as claimed in claim 13, wherein said clock signal generating circuit comprises a frequency divider (125) for dividing a input high-frequency clock signal into a low-frequency clock signal, and a synchronization detecting circuit (126) for establishing a synchronization between said low-fre­quency clock signal and dropped low speed data.

Claim 17

A drop/insert processing circuit comprising: a shift register (120), including n first latching circuits (120-1, 120-2, ... and 120-8), for shifting data of f bits/s in response to a first clock signal having a frequency f; n second latching circuits (122-1, 122-2, ... and 122-8), for incorporating, in response to a second clock signal having a frequency of f/n and a duty ratio of 1:(n-1), outputs of all of the first latching circuits in said shift register; n third latching circuits (121-1, 121-2, ... and 121-8) for incorporating parallel data of f/n bits/sec in response to said second clock signal; data insertion selecting switches (123-1, 123-2, ... and 123-8) for selecting either of outputs of said second latching circuits and outputs of said third latching circuits; a clock signal generating circuit (125 and 126) for dividing said first clock signal, for generating said second clock signal which is synchronous with at least one of outputs of said second latching circuits and for generating an address signal for sequentially selecting outputs of said data insertion selecting switches with a frequency f; and an n:1 selector (124) for sequentially selecting and outputting outputs of said data insertion selecting switches in response to an address signal from said clock signal generating circuit; wherein dropped data of f/n bits/sec is obtained from the output of said third latching circuits and multiplexed data of f/n bits/sec is obtained from the output of said n:1 selector.

Claim 18

A drop/insert processing circuit comprising: a shift register (120), including n first latching circuits (120-1, 120-2, ... and 120-8), for shifting data of f bits/s in response to a first clock signal having a frequency f; n second latching circuits (122-1, 122-2, ... and 122-8), for incorporating, in response to a second clock signal having a frequency of f/n and a duty ratio of 1:(n-1), outputs of all of the first latching circuits in said shift register; n third latching circuits (121-1, 121-2, ... and 121-8) for incorporating parallel data of f/n bits/sec in response to said second clock signal; data insertion selecting switches (123-1, 123-2, ... and 123-8) for selecting either of outputs of said second latching circuits and outputs of said third latching circuits; a clock signal generating circuit (125 and 126) for dividing said first clock signal, for generating said second clock signal which is synchronous with at least one of outputs of said second latching circuits and for generating an address signal for sequentially selecting outputs of said data insertion selecting switches with a frequency f; and an n:1 selector (124) for sequentially selecting and outputting outputs of said data insertion selecting switches in response to an address signal from said clock signal generating circuit; wherein dropped data of f/n bits/sec is obtained from the output of said third latching circuits and multiplexed data of f/n bits/sec is obtained from the output of said n:1 selector.