VDD load dump protection circuit

Claim 2

Power supply load dump protection circuitry for insuring that voltages provided to an operational circuit by a power supply and exceeding a pre-selected voltage are prevented from damaging the operational circuit, the protection circuitry comprising integrated resistive means connected in series between the power supply and the operational circuit to limit the supply current provided to the operational circuit.

Claim 3

Protection circuitry as in claim 1 wherein the resistive means comprises a polysilicon resistor.

Claim 4

Protection circuitry as in claim 1 wherein the resistive means comprises a plurality of parallel-­connected polysilicon resistors.

Claim 5

Protection circuitry as in claim 1 wherein the resistive means are fabricated over dielectric material of sufficient thickness to provide approximately 100V isolation from the operational circuit.

Claim 6

Protection circuitry as in claim 4 wherein the dielectric material is field oxide having a thickness of 6-12K Angstroms.

Claim 7

Power supply load dump protection circuitry for insuring that voltages provided to an operational circuit by a power supply and exceeding a pre-selected voltage are prevented from appearing at an output pad of the operational circuit, the protection circuitry comprising an output pad; a supply voltage pad connected in series between the power supply and the operational circuit for receiving the supply voltage from the power supply; an MOS output pull up transistor of the type that is formed in a semiconductor substrate and comprises source, drain and gate electrodes and wherein the source electrode is connected to the supply pad, the drain electrode is connected to the output pad and the gate electrode is connected to receive an output signal from the operational circuit, the output pull up transistor being constructed to withstand breakdown voltages in excess of the pre-selected voltage between its source and drain and between its source and the semiconductor substrate; and detection means connected between the supply pad and the gate of the output pull up transistor for detecting a supply voltage in excess of the pre-­selected voltage and turning off the output pull up transistor in response thereto.

Claim 8

Power supply load dump protection circuitry for insuring that voltages provided to an operational circuit by a power supply and exceeding a pre-selected voltage are prevented from appearing at an output pad of the operational circuit, the protection circuitry comprising an output pad; a supply voltage pad connected in series between the power supply and the operational circuit for receiving the supply voltage from the power supply; an MOS output pull up transistor of the type that is formed in a semiconductor substrate and comprises source, drain and gate electrodes and wherein the source electrode is connected to the supply pad, the drain electrode is connected to the output pad and the gate electrode is connected to receive an output signal from the operational circuit, the output pull up transistor being constructed to withstand breakdown voltages in excess of the pre-selected voltage between its source and drain and between its source and the semiconductor substrate; and detection means connected between the supply pad and the gate of the output pull up transistor for detecting a supply voltage in excess of the pre-­selected voltage and turning off the output pull up transistor in response thereto.

Claim 9

Protection circuitry as in claim 6 wherein the detection means comprises a switch connected between the source and gate electrodes of the output pull up transistor, and a load dump detection latch having an input connected to the supply pad and an output connected to the switch such that when the voltage at the supply pad exceeds the pre-selected voltage, the latch output causes the switch to close.

Claim 10

Protection circuitry as in claim 7 wherein the switch comprises an MOS switching transistor having its source connected to the supply pad, its drain connected to the gate of the MOS output pull up transistor and its gate connected to receive the latch output such that the switching transistor turns on when the latch output exceeds the pre-selected voltage.

Claim 11

Protection circuitry as in claim 8 wherein the load dump detection latch comprises first resistive means connected between the supply pad and a first node, the first node being connected to the gate of the switching transistor to provide the latch output thereto; a first MOS latch transistor havings its drain connected to the first node, its source connected to ground and its gate connected to a second node; a second MOS latch transistor havings its source connected to the supply pad, its drain connected to the second node and its gate connected to the first node; and second resistive means connected between the second node and ground.

Claim 12

Protection circuitry as in claim 9 and further including third resistive means connected between the drain of the switching transistor and ground.

Claim 13

Protection circuitry as in claim 10 and further including an MOS output pull down transistor havings its drain connected to the output pad, its source connected to ground and its gate connected to receive the output signal from the operational circuit.

Claim 14

An N-well, p-channel transistor structure comprising a substrate of p-type conductivity having a well of n-type conductivity formed at its surface such that a p-n junction is formed between the substrate and the N-well; a first region of p-type conductivity formed in the N-well and connected to receive a supply voltage; a second region of p-type conductivity formed in the N-well in spaced apart relation to the first region and connected to provide an output signal; a layer of dielectric material formed on the surface of the substrate to extend over the well/substrate junction; and a field plate formed on the layer of dielectric material to extend over the well/substrate junction, the field plate being connected to the positive supply such that the presence of the field plate increases the avalanche breakdown voltage of the well/substrate junction.

Claim 15

An N-well, p-channel transistor structure comprising a substrate of p-type conductivity having a well of n-type conductivity formed at its surface such that a p-n junction is formed between the substrate and the N-well; a first region of p-type conductivity formed in the N-well and connected to receive a supply voltage; a second region of p-type conductivity formed in the N-well in spaced apart relation to the first region and connected to provide an output signal; a layer of dielectric material formed on the surface of the substrate to extend over the well/substrate junction; and a field plate formed on the layer of dielectric material to extend over the well/substrate junction, the field plate being connected to the positive supply such that the presence of the field plate increases the avalanche breakdown voltage of the well/substrate junction.

Claim 16

A transistor structure as in claim 12 wherein the dielectric material is silicon dioxide.

Claim 17

Power supply load dump protection circuitry for an integrated supply voltage regulator, the protection circuitry comprising a supply voltage pad; a regulated output voltage pad; a voltage regulator output driver transistor connected between the supply voltage pad and the regulated output voltage pad for controlling the voltage at the regulated output voltage pad at a predetermined voltage; means for generating a reference voltage equal to the predetermined voltage; comparator means connected between the reference voltage reference means and the regulated voltage output pad for maintaining the predetermined voltage at the same level as the reference voltage; and detection means connected between the supply pad and the voltage regulator output driver transistor for detecting a supply voltage in excess of a pre-selected voltage and turning of the voltage regulator output driver transistor in response thereto.

Claim 18

Power supply load dump protection circuitry for an integrated supply voltage regulator, the protection circuitry comprising a supply voltage pad; a regulated output voltage pad; a voltage regulator output driver transistor connected between the supply voltage pad and the regulated output voltage pad for controlling the voltage at the regulated output voltage pad at a predetermined voltage; means for generating a reference voltage equal to the predetermined voltage; comparator means connected between the reference voltage reference means and the regulated voltage output pad for maintaining the predetermined voltage at the same level as the reference voltage; and detection means connected between the supply pad and the voltage regulator output driver transistor for detecting a supply voltage in excess of a pre-selected voltage and turning of the voltage regulator output driver transistor in response thereto.

Claim 19

Protection circuitry as in claim 14 and further including a polysilicon resistor connected between the supply pad and the voltage regulator output driver transistor.

Claim 20

Protection circuitry as in claim 15 wherein the value of the polysilicon resistor is about 100 ohms.

Claim 21

Protection circuitry as in claim 14 wherein the voltage regulator output driver transistor is of the type formed in a semiconductor substrate and comprising source drain and gate electrodes and wherein the source electrode is connected to receive a voltage signal from the supply pad, the drain electrode is connected to the regulated voltage output pad and the gate electrode is connected to receive an output signal from the detection means, the voltage regulator output driver transistor being constructed to withstand breakdown voltages in excess of the pre-selected voltage between its source electrode and drain electrode and between its source electrode and the semiconductor substrate.

Claim 22

Protection circuitry as in claim 17 wherein the detection means comprises a switch connected between the supply pad and the gate electrode of the voltage regulator output driver transistor; and a load dump detection latch having an input connected to the supply pad and an output connected to the switch such that when the voltage at the supply pad exceeds the pre-selected voltage, the latch output causes the switch to close.

Claim 23

Protection circuitry as in claim 18 wherein the switch comprises an MOS switching transistor having its source connected to the supply pad, its drain connected to the gate of the voltage regulator output driver transistor and its gate connected to receive the latch output such that the switching transistor turns on when the latch output exceeds the pre-selected voltage.

Claim 24

Protection circuitry as in claim 19 wherein the load dump detection latch comprises first resistive means connected between the supply pad and a first node, the first note being connected to the gate of the switching transistor to provide the latch output thereto; a first MOS latch transistor having its drain connected to the first node, its source connected to ground and its gate connected to a second node; a second MOS latch transistor having its drain connected to the supply pad, its source connected to the second node and its gate connected to the first node; and second resistive means connected between the second node and ground.

Claim 25

Power supply load dump protection circuitry for insuring that supply voltages applied to the supply pad of an operational circuit and which exceed a pre-­selected voltage level are prevented from damaging the operational circuit and from appearing at an output of the operational circuit, the protection circuitry comprising: (a) resistive means connected between the supply pad the remainder of the operational circuit to limit the supply current to the remainder of the operational circuit; (b) means for preventing the excessive supply voltage from appearing at the output of the operational circuit, the preventive means comprising (i) an MOS output pull up transistor of the type having a source, drain and gate, the source of the output driver transistor being connected to the supply pad, its gate being connected to receive an output signal from the operational circuit and its drain being connected to the output pad; (ii) load dump detection means connected between the source and the gate of the output driver transistor and responsive to the excessive supply voltage to turn off the output driver transistor; (iii) a resistor connected between the gate of the output pull up transistor and the operational circuit, the load dump detection means being connected between one end of the resistor and the gate of the MOS output pull up transistor; and (iv) an output pulldown transistor of the type having a source, drain and gate, the gate of the pulldown transistor being connected to receive the output signal from the operational circuit, its source being connected to ground and its drain being connected between a second end of the resistor and the operational circuit.

Claim 26

Power supply load dump protection circuitry for insuring that supply voltages applied to the supply pad of an operational circuit and which exceed a pre-­selected voltage level are prevented from damaging the operational circuit and from appearing at an output of the operational circuit, the protection circuitry comprising: (a) resistive means connected between the supply pad the remainder of the operational circuit to limit the supply current to the remainder of the operational circuit; (b) means for preventing the excessive supply voltage from appearing at the output of the operational circuit, the preventive means comprising (i) an MOS output pull up transistor of the type having a source, drain and gate, the source of the output driver transistor being connected to the supply pad, its gate being connected to receive an output signal from the operational circuit and its drain being connected to the output pad; (ii) load dump detection means connected between the source and the gate of the output driver transistor and responsive to the excessive supply voltage to turn off the output driver transistor; (iii) a resistor connected between the gate of the output pull up transistor and the operational circuit, the load dump detection means being connected between one end of the resistor and the gate of the MOS output pull up transistor; and (iv) an output pulldown transistor of the type having a source, drain and gate, the gate of the pulldown transistor being connected to receive the output signal from the operational circuit, its source being connected to ground and its drain being connected between a second end of the resistor and the operational circuit.

Claim 27

In a process for fabricating MOS transistors in a substrate of P-conductivity type, the sequential steps of defining field oxide regions and well regions of N-conductivity; growing a gate oxide layer about 700 Angstrom thick in selected areas cleared of field oxide; removing portions of the 700 Angstrom gate oxide layer; and growing a second gate oxide layer about 400 Angstrom thick resulting in 400 Angstrom gate oxide in those portions removed from the 700 Angstrom gate oxide and about 1000 Angstrom gate oxide in the remaining portions of the 700 Angstrom gate oxide.

Claim 28

In a process for fabricating MOS transistors in a substrate of P-conductivity type, the sequential steps of defining field oxide regions and well regions of N-conductivity; growing a gate oxide layer about 700 Angstrom thick in selected areas cleared of field oxide; removing portions of the 700 Angstrom gate oxide layer; and growing a second gate oxide layer about 400 Angstrom thick resulting in 400 Angstrom gate oxide in those portions removed from the 700 Angstrom gate oxide and about 1000 Angstrom gate oxide in the remaining portions of the 700 Angstrom gate oxide.