EP0305775A2 — FSK demodulation circuit

Claim 1

Independent Claim 178 words

An FSK demodulation circuit having: a phase detection means which receives as input an FSK modulated reception signal r(t) and performs phase detection on the same so as to produce quadrature I-ch and Q-ch analog base band signals and which further converts said analog base band signal to a digital signal and outputs an I-ch pulse train D I and Q-ch pulse train D Q and a data reproducing means which reproduces the original data from the said I-ch pulse train D I and Q-ch pulse train D Q to output a reproduced data D out , characterized in that said data reproducing means comprises: at least two sampling means which uses the edge of one pulse train of the said pulse trains D I and D Q and samples at mutually different timings the logic of the other pulse train, and a decision means which receives as input the sample outputs from the said at least two sampling means and determines the logic of said reproduced data D out by a predetermined decision operation on the same.

Claim 2

Dependent Claim 178 words

An FSK demodulation circuit having: a phase detection means which receives as input an FSK modulated reception signal r(t) and performs phase detection on the same so as to produce quadrature I-ch and Q-ch analog base band signals and which further converts said analog base band signal to a digital signal and outputs an I-ch pulse train D I and Q-ch pulse train D Q and a data reproducing means which reproduces the original data from the said I-ch pulse train D I and Q-ch pulse train D Q to output a reproduced data D out , characterized in that said data reproducing means comprises: at least two sampling means which uses the edge of one pulse train of the said pulse trains D I and D Q and samples at mutually different timings the logic of the other pulse train, and a decision means which receives as input the sample outputs from the said at least two sampling means and determines the logic of said reproduced data D out by a predetermined decision operation on the same.

Claim 3

Dependent Claim 148 words

An FSK demodulation circuit according to claim 1, wherein: said at least two sampling means are comprised of a first sampling means which uses the edge of the other said pulse train and samples the logic of the one said pulse train to obtain a first sample output Q₁ and a second sampling means which uses the edge of the said one pulse train and samples the inverted logic of the said other pulse train to obtain a second sample output Q₂ and said decision means comprises a coincidence detection part which detects coincidence or noncoincidence of the logics of said first and second sample outputs Q₁ and Q₂ and a latch part which forms the logic of said reproduced data D out using the current logic upon coincidence and forms the logic of said reproduced data D out with the logic just before, held internally, upon noncoincidence.

Claim 4

Dependent Claim 56 words

An FSK demodulation circuit according to claim 2, which is provided with a delay means for giving a predetermined delay to said sample output Q₁ and applying the same to said latch circuit, said delay means giving a delay time set substantially equal to the time required for detection of coincidence at said coincidence detection part.

Claim 5

Dependent Claim 70 words

An FSK demodulation circuit according to claim 2, wherein said first and second sampling means are comprised of first and second D-type flip-flops receiving as D inputs said first and second pulse trains D I and D Q and as clock inputs the other pulse trains, and said sample outputs Q₁ and Q₂ are obtained from the Q output and the Q output of said first and second D-type flip-flops.

Claim 6

Dependent Claim 71 words

An FSK demodulation circuit according to claim 2, wherein said coincidence detection part is comprised of an EXOR gate receiving as two inputs said first and second sample outputs Q₁ and Q₂ and an inverter leading to the EXOR gate output and, upon coincidence of Q₁ and Q₂ , outputs logic "1" from said inverter and upon noncoincidence of Q₁ and Q₂ , outputs logic "0" and controls said latch part.

Claim 7

Dependent Claim 149 words

An FSK demodulation circuit according to claim 1, wherein: said at least two sampling means are comprised of a third sampling means which uses the leading edge of the other said pulse train and samples the logic of the one said pulse train to obtain a first sample output Q₁ and a fourth sampling means which uses the trailing edge of the said other pulse train and samples the inverted logic of the said one pulse train to obtain another first sample output Q₁′ and said decision means comprises a coinci dence detection part which detects coincidence or noncoincidence of the logics of said first sample outputs Q₁ and Q₁′ and a latch part which forms the logic of said reproduced data D out using the current logic upon coincidence and forms the logic of said reproduced data D out with the logic just before, held internally, upon noncoincidence.

Claim 8

Dependent Claim 56 words

An FSK demodulation circuit according to claim 6, which is provided with a delay means for giving a predetermined delay to said sample output Q₁ and applying the same to said latch part, said delay means giving a delay time set substantially equal to the time required for detection of coincidence at said coincidence detection part.

Claim 9

Dependent Claim 103 words

An FSK demodulation circuit according to claim 6, wherein said third sampling means is comprised of a third D-type flip-flop receiving as a D input and clock input said first and second pulse trains D I and D Q , respectively, and said fourth sampling means is comprised of a fourth D-type flip-flop receiving as a D input said first pulse train D I and as a clock input said second pulse train D Q passed through an inverter, said second sample outputs Q₁ and Q₁′ being obtained from the Q output and the Q output of said third and fourth D-type flip-flops.

Claim 10

Dependent Claim 67 words

An FSK demodulation circuit according to claim 6, wherein said coincidence detection part is comprised of an EXOR gate receiving as two inputs said first sample outputs Q₁ and Q₁′ and an inverter leading to the EXOR gate output and, upon coincidence of Q₁ and Q₁′, outputs logic "1" from said inverter and upon noncoincidence of Q₁ and Q₁′, outputs logic "0" and controls said latch part.

Claim 11

Dependent Claim 173 words

An FSK demodulation circuit according to claim 1, wherein: said at least two sampling means are comprises of fifth, sixth, seventh, and eighth sampling means which use the leading edge and the trailing edge of the other said pulse train D Q and sample the logic or inverted logic of the said one pulse train D I and use the leading edge and the trailing edge of the said one pulse train D I and sample the logic or inverted logic of the said other pulse train D Q to obtain four sample outputs Q₅ , Q₆ , Q₇ , and Q₈ and said decision means comprises a majority logic decision means which makes a majority logic decision on the four sample outputs Q₅ to Q₈ and outputs the decision results and a holding means which, when the said decision result is of a majority of the logic "1", transmits "1" as the logic of the reproduced data D out and, when it is of a majority of the logic "0", transmits "0".

Claim 12

Dependent Claim 89 words

An FSK demodulation circuit according to claim 10, wherein when the said decision result is of the same number of logics "1" and "0", the said holding means outputs the previously held logic as it is and uses it as the logic of the reproduced data D out 12. An FSK demodulation circuit according to claim 11, wherein a delay means is provided at the stage before said holding means, said delay means giving a delay time set substantially equal to the time required for said majority logic decision.

Claim 13

Dependent Claim 128 words

An FSK demodulation circuit according to claim 10, wherein said fifth sampling means is comprised of fifth and seventh D-type flip-flops and receives as a D input and clock input said first and second pulse trains D I and D Q , respectively, and said seventh sampling means receives as a D input and clock input said pulse trains D I and D Q , respectively, through inverters, and said sixth sampling means is comprised of sixth and eighth D-type fli-flop and receives as a D input and clock input said second and first pulse trains D Q and Q I , respectively, and said eighth sampling means receives as a D input and clock input said pulse trains D Q and D I , respectively, through inverters.

Claim 14

Dependent Claim 60 words

An FSK demodulation circuit according to claim 10, wherein said majority logic decision means comprises a memory which receives as address inputs said sample outputs Q₅ to Q₈ and a logic predetermined in accordance with combinations of logics "1" and "0" of said sample outputs Q₅ to Q₈ is read out from said memory and transmitted to said holding means.

Claim 15

Dependent Claim 18 words

An FSK demodulation circuit according to claim 10, wherein said holding means is comprised of a latch circuit.

Claim 16

Dependent Claim 20 words

An FSK demodulation circuit according to claim 10, wherein said majority logic decision means is comprised of a logic gate.

Claim 17

Dependent Claim 21 words

An FSK demodulation circuit according to claim 10, wherein said majority logic decision means is comprised of an analog adder circuit.

Claim 18

Dependent Claim 177 words

An FSK demodulation circuit according to claim 1, wherein: said at least two sampling means are comprised of ninth, 10th, and 11th sampling means which use the leading edge and the trailing edge of the said other pulse train D Q and sample the logic or inverted logic of the said one pulse train D I and use the leading edge and the trailing edge of the said one pulse train D I and sample the logic or inverted logic of the said other pulse train D Q to obtain three sample outputs Q₉ , Q₁₀ , and Q₁₁ and said decision means comprises a majority logic decision means which makes a majority logic decision on the three sample outputs Q₉ , Q₁₀ , and Q₁₁ and outputs the decision results and a holding means which, when the said decision result is of a number of logics "1" greater than "0", transmits "1" as the logic of the reproduced data D out and, when it is of a number of logics "0" greater than "1", transmits "0".

Claim 19

Dependent Claim 112 words

An FSK demodulation circuit according to claim 18, wherein the said ninth sampling means is comprised of a ninth D-type flip-flop and receives as its clock input and D input the said first and second pulse trains D I and D Q , said 10th sampling means is comprised of a tenth D-type flip-flop and receives as its clock input and D input the said pulse trains D Q and D I , and said 11th sampling means is comprised of a 11th D-type flip-flop and receives as its D input and clock input the said pulse train D I and the pulse train D Q which has passed through an inverter.

Claim 20

Dependent Claim 68 words

An FSK demodulation circuit according to claim 18, wherein said majority logic decision means is comprised of a memory which receives as address inputs said sample outputs Q₉ , Q₁₀ , and Q₁₁ and a logic predetermined in accordance with combinations of logics "1" and "0" of said sample outputs Q₉ , Q₁₀ , and Q₁₁ is read out from said memory and transmitted to said holding means.

FSK demodulation circuit

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag