Patent EP0304839A2 successfully refreshed from Google Patents.
EP0304839A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for fabricating insulated gate semiconductor device
Assignee: Hitachi Ltd
•
Filing: 1988-08-22
•
Granted: —
•
Expires: 2008-08-22
Abstract
Abstract A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n--Iayer (12) surface, forming p-well layers (13) in the n‾-layer using the insulated gates as masks, forming phosphosilicate glass layers (24) on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n -source (15) layer.
Inventors
- 👤 Mutsuhiro Mori
- 👤 Tomoyuki Tanaka
- 👤 Yasumichi Yasuda
- 👤 Yasunori Nakano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/411; H10D12/441; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
211 words
A method for fabricating a semiconductor device including a plurality of well layers of the other conductivity type formed apart from one another so as to be exposed on the surface of a semiconductor layer of one conductivity type; source layers of the one conductivity type each formed in each of the well layers so that their surface are exposed; insulated gates each consisting of three layers of a gate oxide film (15), a gate electrode (21) and an insulating film (22) on the exposed portion of the semiconductor layer and the exposed portions of the well layers on both sides thereof, and a source electrode (42) kept in contact with the exposed surface of the well layers and the source layers and extended over the insulated gate, characterized by comprising the steps: forming the insulated gates at predetermined intervals on the surface of the semiconductor layer, forming the well layers of the other conductivity type in the semiconductor layer using the insulated gates as masks, forming films doped with impurities of the one conductivity type on the side walls of the insulated gates; and diffusing the impurities from the films doped with the one conductivity type impurities into the well layers to form source layers of the one conductivity type.
Claim 2
Independent Claim
211 words
A method for fabricating a semiconductor device including a plurality of well layers of the other conductivity type formed apart from one another so as to be exposed on the surface of a semiconductor layer of one conductivity type; source layers of the one conductivity type each formed in each of the well layers so that their surface are exposed; insulated gates each consisting of three layers of a gate oxide film (15), a gate electrode (21) and an insulating film (22) on the exposed portion of the semiconductor layer and the exposed portions of the well layers on both sides thereof, and a source electrode (42) kept in contact with the exposed surface of the well layers and the source layers and extended over the insulated gate, characterized by comprising the steps: forming the insulated gates at predetermined intervals on the surface of the semiconductor layer, forming the well layers of the other conductivity type in the semiconductor layer using the insulated gates as masks, forming films doped with impurities of the one conductivity type on the side walls of the insulated gates; and diffusing the impurities from the films doped with the one conductivity type impurities into the well layers to form source layers of the one conductivity type.
Claim 3
Dependent Claim
57 words
A method for fabricating an insulated gate semiconductor device according to Claim 1, characterized in that the step of forming films doped with one conductivity type impurities includes the substeps of forming a doped film on the entire surface of the exposed portions of the insulated gates and the well layers and of anisotropic-dry-etching the doped film.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.