Abstract A digital communication system comprises a transmitter including a (1, 0, -1) precoder (11) for precoding a unipolar input digital data stream and a bipolar converter (12) for converting the output signal of the (1, 0, -1) precoder into a bipolar signal. The bipolar signal is transmitted through a metallic transmission line (13) to a receiver. The receiver comprises an analog-to-digital converter (14) for converting the multilevel of the transmitted signal to digital form, and a line equalization filter (15) for equalizing losses encountered during propagation through the transmission line. A (1,1) equalizer (16) is provided for equalizing the output signal of the line equalization filter. A clock recovery circuit (18) derives sample timing pulses from the output of the line equalization filter. A decoder (17) responds to the sample timing pulses to detect symbols from the output signal of the (1, 1) equalizer to generate a replica of the original digital data stream.
A digital communication system comprising: a (1, 0, -1) precoder for precoding a unipolar input digital data stream; a bipolar converter for converting the output signal of said (1, 0, -1) precoder into a bipolar signal and transmitting the bipolar signal through a transmission line to a receive end of the system; a line equalization filter at said receive end for equalizing the losses of the transmitted signal experienced during propagation through said transmission line; a (1, 1) equalization circuit for equalizing the output signal of said line equalization filter; a decoder for detecting symbols from the output signal of said (1, 1) equalization circuit to generate a replica of said digital data stream; and a clock recovery circuit for deriving sample timing pulses from the output signal of said line equalization filter and supplying said timing pulses to said decoder.
Claim 2
Dependent Claim
141 words
A digital communication system comprising: a (1, 0, -1) precoder for precoding a unipolar input digital data stream; a bipolar converter for converting the output signal of said (1, 0, -1) precoder into a bipolar signal and transmitting the bipolar signal through a transmission line to a receive end of the system; a line equalization filter at said receive end for equalizing the losses of the transmitted signal experienced during propagation through said transmission line; a (1, 1) equalization circuit for equalizing the output signal of said line equalization filter; a decoder for detecting symbols from the output signal of said (1, 1) equalization circuit to generate a replica of said digital data stream; and a clock recovery circuit for deriving sample timing pulses from the output signal of said line equalization filter and supplying said timing pulses to said decoder.
Claim 3
Dependent Claim
40 words
A digital communication system as claimed in claim 1, further comprising an analog-to-digital converter for converting said bipolar signal transmitted through said transmission line into a digital data stream and applying the digital data stream to said line equalization filter.
Claim 4
Dependent Claim
232 words
A digital communication system as claimed in claim 1 or 2, wherein said transmission line has a √f attenuation characteristic, where f represents the frequency of the signal transmitted by the transmission line; wherein said (1, 0, -1) precoder comprises a modulo-2 adder for modulo-2 summing said unipolar input digital data stream with a second signal, and a delay line for introducting a delay time 2T to an output signal from said modulo-2 adder and supplying the delayed signal to said modulo-2 adder as said second signal, where T represents intervals between successive symbols; wherein said bipolar converter comprises a delay line for introducing a delay time T to the output signal of said precoder and a subtractor for subtracting the output of the last-mentioned delay line from the output of said precoder; wherein said (1, 1) equalizer comprises a delay line for introducing a delay time T to the output signal of said line equalizing filter and an adder for summing the output signal of the last-mentioned delay line with the output signal of said line equalizing filter, said (1, 1) equalizer suppressing higher frequency components of the output signal of said line equalizing filter; and wherein said decoder comprises means for providing modulo-2 conversion on the output of said (1, 1) equalizer so that bipolar format of the output signal of said (1, 1) equalizer is converted to unipolar format.
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