Patent EP0303341A2 successfully refreshed from Google Patents.
EP0303341A2
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EP
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Output buffer circuits
Assignee: Advanced Micro Devices Inc
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Filing: 1988-06-15
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Granted: —
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Expires: 2008-06-15
Abstract
Abstract An output buffer includes a pull-up transistor (N1), a first pull-down transistor (N3), a second pull-down transistor (N8), and a logic circuit (15). The logic circuit (15) is responsive to a data input signal making a high-to-low transition and the output signal making a high-to-low transition for maintaining the second pull-down transistor (N8) turned-off until after an output node has made the high-to-low transition, thereby reducing significantly the ground bounce noise.
Inventors
- 👤 Bor-Tay Wu
- 👤 Wayne W. Yip Wong
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 13:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
305 words
An output buffer for providing an output signal at an output node which has a significant reduction in ground bounce noise, comprising: pull-up circuit means responsive to a first control signal for generating slowly a transition from a low logic level to a high logic level at the output node; said pull-up circuit means including a pull-up transistor having one of its main electrodes coupled to a first power supply terminal, its other main electrode coupled to the output node, and its control electrode coupled to receive the first control signal; pull-down circuit means responsive to second and third control signals for generating slowly a transition from the high logic level to the low logic level at the output node; said pull-down circuit means including a first pull-down transistor having one of its main electrodes coupled to a second power supply terminal, its other main electrode copled to the output node, and its control electrode coupled to receive the second control signal; said pull-down circuit means further including a second pull-down transistor having one of its main electrodes coupled to the second power supply terminal, its other main electrode coupled to the output node, and its control electrode copled to receive the third control signal; first logic means responsive to a data input signal making a low-to-high transition and the output signal making a low-to-high transition for generating the first control signal; second logic means responsive to the data input signal making a high-to-low transition and the output signal making a high-to-low transition for generating the second control signal; and third logic means responsive to the data input signal making the high-to-low transition and the output signal making the high-to-low transition for maintaining the second pull-down transistor turned-off until after the output node has made the high-to-low transition, thereby reducing significantly the ground bounce noise.
Claim 2
Dependent Claim
305 words
An output buffer for providing an output signal at an output node which has a significant reduction in ground bounce noise, comprising: pull-up circuit means responsive to a first control signal for generating slowly a transition from a low logic level to a high logic level at the output node; said pull-up circuit means including a pull-up transistor having one of its main electrodes coupled to a first power supply terminal, its other main electrode coupled to the output node, and its control electrode coupled to receive the first control signal; pull-down circuit means responsive to second and third control signals for generating slowly a transition from the high logic level to the low logic level at the output node; said pull-down circuit means including a first pull-down transistor having one of its main electrodes coupled to a second power supply terminal, its other main electrode copled to the output node, and its control electrode coupled to receive the second control signal; said pull-down circuit means further including a second pull-down transistor having one of its main electrodes coupled to the second power supply terminal, its other main electrode coupled to the output node, and its control electrode copled to receive the third control signal; first logic means responsive to a data input signal making a low-to-high transition and the output signal making a low-to-high transition for generating the first control signal; second logic means responsive to the data input signal making a high-to-low transition and the output signal making a high-to-low transition for generating the second control signal; and third logic means responsive to the data input signal making the high-to-low transition and the output signal making the high-to-low transition for maintaining the second pull-down transistor turned-off until after the output node has made the high-to-low transition, thereby reducing significantly the ground bounce noise.
Claim 3
Dependent Claim
18 words
An output buffer as claimed in Claim 1, wherein said pull-up transistor is an N-channel field-effect transistor (N1).
Claim 4
Dependent Claim
21 words
An output buffer as claimed in Claim 2, wherein said first and second pull-down transistors are N-channel field-effect transistors (N3, N8).
Claim 5
Dependent Claim
18 words
An output buffer as claimed in Claim 1, wherein said pull-up transistor is a P-channel, field-effect transistor (P1).
Claim 6
Dependent Claim
21 words
An output buffer as claimed in Claim 4, wherein said first and second pull-down transistors are N-channel field-effect transistors (N3, N8).
Claim 7
Dependent Claim
113 words
An output buffer as claimed in Claim 3, wherein said first logic means comprises a first NOR logic gate (13) having a first input coupled to the data input signal, a second input coupled to the output signal, and an output; a first N-channel control transistor (N5) having its drain coupled to the first power supply terminal (24), its source coupled to the gate of the pull-up transistor (N1), and its gate coupled to the output of said first NOR gate (13); and a second NOR logic gate (12) having first and second inputs coupled to the data input signal and an output also coupled to the gate of said pull-up transistor (N1).
Claim 8
Dependent Claim
111 words
An output buffer as claimed in Claim 6, wherein said second logic means comprises an AND logic gate (17) having a first input coupled to the output signal, a second input coupled to the data input signal, and an output; a second N-channel control transistor (N7) having its drain coupled to the output node, its source coupled to the gate of said first pull-down transistor (N3), and its gate coupled to the output of said AND logic gate (17); and a third NOR logic gate (14) having first and second inputs coupled to the data input signal and an output also coupled to the gate of said first pull-down transistor (N3).
Claim 9
Dependent Claim
51 words
An output buffer as claimed in Claim 7, wherein said third logic means comprises a fourth NOR logic gate (15) having a first input coupled to the output signal, a second input coupled to the data input signal, and an output coupled to the gate of said second pull-down transistor (N8).
Claim 10
Dependent Claim
46 words
An output buffer as claimed in Claim 3, wherein the size of said first pull-down transistor (N3) is equal in size to said pull-up transistor (N1) and the size of said second pull-down transistor (N8) is equal or larger in size than said pull-down transistor (N3).
Claim 11
Dependent Claim
46 words
An output buffer as claimed in Claim 5, wherein the size of said first pull-down transistor (N3) is smaller in size than said pull-up transistor (P1) and the size of said second pull-down transistor (N8) is equal or larger in size than said pull-down transistor (N3).
Claim 12
Dependent Claim
110 words
An output buffer as claimed in Claim 5, wherein said first logic means comprises a first NOR logic gate (13) having a first input coupled to the data input signal, a second input coupled to the output signal, and an output; a first N-channel control transistor (N5) having its source coupled to the output node (A), its drain coupled to the gate of the pull-up transistor (P1), and its gate coupled to the output of said first NOR gate (13); and a NAND logic gate (12b) having first and second inputs coupled to the data input signal and an output also coupled to the gate of said pull-up transistor (P1).
Claim 13
Dependent Claim
111 words
An output buffer as claimed in Claim 11, wherein said second logic means comprises an AND logic gate (17) having a first input coupled to the output signal, a second input coupled to the data input signal, and an output; a second N-channel control transistor (N7) having its drain coupled to the output node, its source coupled to the gate of said first pull-down transistor (N3), and its gate coupled to the output of said AND logic gate (17); and a second NOR logic gate (14) having first and second inputs coupled to the data input signal and an output also coupled to the gate of said first pull-down transistor (N3).
Claim 14
Dependent Claim
51 words
An output buffer as claimed in Claim 12, wherein said third logic means comprises a third NOR logic gate (15) having a first input coupled to the output signal, a second input coupled to the data input signal, and an output coupled to the gate of said second pull-down transistor (N8).
Claim 15
Dependent Claim
192 words
An output buffer for providing an output signal at an output node which has a significant reduction in ground bounce noise, comprising: pull-up circuit means responsive to a first control signal for generating slowly a transition from a low logic level to a high logic level at the output node; pull-down circuit means responsive to second and third control signals for generating slowly a transition from the high logic level to the low logic level at the output node; first logic means responsive to a data input signal making a low-to-high transition and the output signal making a low-to-high transition for generating the first control signal; second logic means responsive to the data input signal making a high-to-low transition and the output signal making a high-to-low transition for generating the second control signal; and third logic means having first and second current paths respectively responsive to the data input signal making the high-to-low transition and the output signal making the high-to-low transition for generating the third control signal to maintain said second current path turned-off until after the output node has made the high-to-low transition, thereby reducing significantly the ground bounce noise.
Claim 16
Dependent Claim
192 words
An output buffer for providing an output signal at an output node which has a significant reduction in ground bounce noise, comprising: pull-up circuit means responsive to a first control signal for generating slowly a transition from a low logic level to a high logic level at the output node; pull-down circuit means responsive to second and third control signals for generating slowly a transition from the high logic level to the low logic level at the output node; first logic means responsive to a data input signal making a low-to-high transition and the output signal making a low-to-high transition for generating the first control signal; second logic means responsive to the data input signal making a high-to-low transition and the output signal making a high-to-low transition for generating the second control signal; and third logic means having first and second current paths respectively responsive to the data input signal making the high-to-low transition and the output signal making the high-to-low transition for generating the third control signal to maintain said second current path turned-off until after the output node has made the high-to-low transition, thereby reducing significantly the ground bounce noise.
Claim 17
Dependent Claim
19 words
An output buffer as claimed in Claim 14, wherein said pull-up circuit means comprises an N-channel field-effect transistor (N1).
Claim 18
Dependent Claim
19 words
An output buffer as claimed in Claim 15, wherein said pull-down circuit means comprises N-channel field-effect transistors (N3, N8).
Claim 19
Dependent Claim
19 words
An output buffer as claimed in Claim 14, wherein said pull-up circuit means comprises a P-channel, field-effect transistor (P1).
Claim 20
Dependent Claim
19 words
An output buffer as claimed in Claim 17, wherein said pull-down circuit means comprises N-channel field-effect transistors (N3, N8).
Claim 21
Dependent Claim
40 words
An output buffer as claimed in Claim 16, wherein the size of said transistor (N3) is equal in size to said transistor (N1) and the size of said transistor (N8) is equal or larger in size than said transistor (N3).
Claim 22
Dependent Claim
40 words
An output buffer as claimed in Claim 18, wherein the size of said transistor (N3) is smaller in size than said transistor (P1) and the size of said transistor (N8) is equal or larger in size than said transistor (N3).
References Cited (Backward Citations)
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