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EP0302999A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Out-of-sequence operand fetches

Assignee: International Business Machines Corp
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Filing: 1988-04-21
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Granted: —
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Expires: 2008-04-21
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Abstract

Abstract Monitoring apparatus is provided to allow out-­of-sequence fetching of operands while preserving the appearance of in-sequence fetching to the processor of a computer. The key elements include a stack (119) of N entries holding the addresses of the last M, where M is less than or equal to N, out-of-sequence fetches. A comparator (103) is provided for comparing addresses in the stack with a test address. This test address is supplied via an OR gate (107) as either store addresses or cross-invalidate addresses, the latter being for a multiprocessor system. The addresses in the stack that compare with the test address are set as invalid. In addition, all addresses in the stack are set as invalid on the occurrence of a cache miss or serializing instruction. Finally, a select and check entry function (113) associates an address in the stack with the instruction it represents and deletes the address from the stack when the instruction is handled in its proper sequence.

Inventors

  • 👤 Philip George Emma
  • 👤 Iii Joshua Wilson Knight
  • 👤 James Herbert Pomerene
  • 👤 Rudolph Nathan Rechtschaffen
  • 👤 Frank John Sparacio

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 13:40
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F9/3824; G06F9/3834

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 126 words
Apparatus for monitoring out-of-sequence fetches in a computer having means to fetch operands and execute instructions in accordance therewith, comprising: a stack having N entries for holding the addresses of the last M out of sequence fetches, where M is less than or equal to N, each of said addresses having associated therewith a valid bit; comparison means for comparing addresses in said stack with a predetermined test address; means for setting invalid the valid bit of addresses that compare with said test address; means for selecting store addresses and cross- invalidate addresses as said pre­determined test address; and means for associating an address in the stack with an instruction it represents and for deleting said address when said instruction is handled in its proper sequence.
Claim 2
Dependent Claim 126 words
Apparatus for monitoring out-of-sequence fetches in a computer having means to fetch operands and execute instructions in accordance therewith, comprising: a stack having N entries for holding the addresses of the last M out of sequence fetches, where M is less than or equal to N, each of said addresses having associated therewith a valid bit; comparison means for comparing addresses in said stack with a predetermined test address; means for setting invalid the valid bit of addresses that compare with said test address; means for selecting store addresses and cross- invalidate addresses as said pre­determined test address; and means for associating an address in the stack with an instruction it represents and for deleting said address when said instruction is handled in its proper sequence.
Claim 3
Dependent Claim 34 words
The apparatus for monitoring out-of-sequence fetches recited in claim 1 further comprising means for setting the valid bits for all address in said fetch stack to invalid on the occurrence of a cache miss.
Claim 4
Dependent Claim 34 words
The apparatus for monitoring out-of-sequence fetches recited in claim 1 further comprising means for setting the valid bits for all addresses in said fetch stack to invalid on the occurrence of a serializing instruction.
Claim 5
Dependent Claim 42 words
The apparatus for monitoring out-of-sequence fetches recited in claim 1 further comprising means for setting the valid bits for all addresses in said fetch stack to invalid on the occurrence of at least one of a cache miss or a serializing instruction.
Claim 6
Dependent Claim 109 words
The apparatus for monitoring out-of-sequence fetches recited in claim 1 wherein each of said addresses held in said stack further has a full/empty bit associated therewith, said full/empty bit being set to full when there is an entry in stack for the address, and said means for associating an address in the stack with an instruction comprises: means for selecting an entry in said stack corresponding to a current instruction; and means for checking the full/empty bit and the valid bit for the selected entry and signal ing that corrective action is required when the full/empty bit is set to full and the valid bit is set to invalid.
Claim 7
Dependent Claim 48 words
The apparatus for monitoring out-of-sequence fetches as recited in claim 5 further com­prising: means for detecting and signalling an overflow condition of said stack; and means for setting the valid bits of all addresses in said stack to invalid in response to the signalling of an overflow condition.

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