Method of manufacturing CMOS EPROM memory cells

Claim 1

Method of manufacturing CMOS EPROM memory cells, comprising the steps of: - implementation, in a substrate (101) of semiconductor material having a first type of conductivity, defining at least one memory portion and one driving portion, wherein said memory portion accomodates a plurality of active memory regions (118) adapted to form memory cells and said driving portion comprises active driving regions comprising zones (107) having a second type of conductivity, substantially opposite to the first, and adapted to form a plurality of CMOS transistors including a pair of complementary MOS transistors each having source, drain and gate regions, of a first oxide layer (119) on the surface of said substrate (101), - deposition of a second layer (124) of polycrystalline semiconductor material on said first layer at least at said active memory regions (118), - formation of a third layer (126) of dielectric material at least over said second layer (124), - deposition of a fourth layer (128) of polycrystalline semiconductor material, - masking of said fourth layer (128) by means of a first mask (31) adapted to cover the gate regions (128′,130′) of the memory cells and of the CMOS transistors, - removal of the uncovered portions of said fourth layer (128) to form gate regions (128′,130′) of said memory cells and of said transistors, characterized by the steps of: - removal of said first mask (31), - selective masking of the active driving regions (107) by means of a second mask (140) having windows at the active memory regions (118) and at first portions (107) of the active driving regions adapted to define a first transistor of each pair of complementary transistors, - introduction of first doping impurities into said substrate (101) at said first portions (107) of the active driving regions for the formation of source and drain regions (142) of said first transistors, said active memory regions being screened by said second (124) and third layer (126), - selective removal of said third layer (126) of said active memory regions (118) except for the gate regions (128′) of the memory cells, - removal of said second mask (140), - selective masking of the active driving regions (107) by means of a third mask (135) having windows at the active memory regions (118) and at second portions of the active driving regions adapted to define a second transistor of each pair of complementary transistors, - removal of said second layer (124) at the active memory regions (118) except for the gate regions (128′) of said memory cells, - introduction of second doping impurities into said substrate (101) at said second portions of the active driving regions and at said active memory regions (118) for the formation of source and drain regions (137;148) of said second transistors and of the memory cells, - removal of said third mask (135), - formation of a protective insulation layer (151), of the contacts (158′) and of the metallizations (160), as well as of a passivation layer, in a per se known manner.