Register management system in a computer processor with out-of-sequence instruction execution

Claim 2

A computer system which has provision for out of sequence instruction execution characterized by a register array (RA) means of m hardware registers in a system architecture requiring that n addressable registers be provided, where m is greater than n, an instruction execution means for executing instructions in said register array (RA) and being connected to send and receive information to said register array (RA), a processor store for holding instructions and data and for providing instructions and data to said instruction execution means, an instruction control means for controlling the movement of instructions from said processor store to said instruction execution means, said instruction control means being connected to said processor store and said instruction execution means, and logic unit means connected with said register array means for assigning a hardware register equivalent location for each addressable register during instruction execution and where an additional hardware register location or locations is assigned equivalent to the same addressable register during execution of an instruction out of order so that both a new value and an old value or values are maintained during out of order instruction execution.

Claim 3

The system of Claim 1, characterized in that said instruction execution means is comprised of at least one general purpose execution unit and at least one special purpose processing unit.

Claim 4

The system of Claim 1 further characterized by an array control list (ACL) connected to and controlled by said logic unit means which records the assignment information for each of the m registers in the RA, and a decode register assignment list (DRAL) connected to and controlled by said logic unit means which records the status of each of the addressable registers.

Claim 5

The system of Claim 3 further characterized by a back-up register assignment list BRAL connected to said DRAL and which receives and copies the contents of the DRAL upon occurrence of a predetermined condition and which can copy said contents back into the DRAL upon occurrence of a further selected condition thereby allowing recovery of the computer system to a previously existing status.

Claim 6

The system of Claim 4 further characterized by a plurality of BRAL's each of which independently copies the contents of the DRAL upon occurrence of predetermined independent conditions and which can copy said contents back into the DRAL upon occurrence of predetermined independent conditions thereby allowing recovery of the computer system to a previously existing status.

Claim 7

A computer system which has provision for out of sequence instruction execution and conditional branch instructions characterized by memory means for storing instructions and data, a register array (RA) of m registers in a system architecture having n addressable registers, where m is greater than n, said register array (RA) being connected to receive and send information to and from said memory means, an array control list (ACL) means having m positions where each position is a status identifying field associated with one of the m registers in said register array (RA), said ACL means being connected to receive and send status signals to and from said register array (RA), a decode register assignment list (DRAL) means connected with said register array (RA) for keeping track of instructions, said DRAL means having n positions where each position is a status identifying field associated with one of the n addressable registers in the system architecture, said DRAL means being connected to receive and send status signals to and from said register array (RA), at least one instruction execution means for receiving instructions and data and for producing results of instructions, said instruction unit being connected to provide status signals to said ACL means and said DRAL means, instruction decoding and register means for receiving instructions from said memory means and connected to said instruction execution means for sending decoded instructions to be executed, said instruction decoding register means being connected to send status signals to said DRAL means and said ACL means, wherein said ACL means and said DRAL means receive instruction status signals and maintain register status information for at least some old values for some of said n addressable registers while out of sequence and conditional branch instructions complete execution and provide new values for assigned positions of said n addressable registers by using multiple positions in the register array (RA) and wherein the old values for the assigned positions of said n addressable registers may be restored up until the time said new positions are assigned a complete of execution status.

Claim 8

A computer system which has provision for out of sequence instruction execution and conditional branch instructions characterized by memory means for storing instructions and data, a register array (RA) of m registers in a system architecture having n addressable registers, where m is greater than n, said register array (RA) being connected to receive and send information to and from said memory means, an array control list (ACL) means having m positions where each position is a status identifying field associated with one of the m registers in said register array (RA), said ACL means being connected to receive and send status signals to and from said register array (RA), a decode register assignment list (DRAL) means connected with said register array (RA) for keeping track of instructions, said DRAL means having n positions where each position is a status identifying field associated with one of the n addressable registers in the system architecture, said DRAL means being connected to receive and send status signals to and from said register array (RA), at least one instruction execution means for receiving instructions and data and for producing results of instructions, said instruction unit being connected to provide status signals to said ACL means and said DRAL means, instruction decoding and register means for receiving instructions from said memory means and connected to said instruction execution means for sending decoded instructions to be executed, said instruction decoding register means being connected to send status signals to said DRAL means and said ACL means, wherein said ACL means and said DRAL means receive instruction status signals and maintain register status information for at least some old values for some of said n addressable registers while out of sequence and conditional branch instructions complete execution and provide new values for assigned positions of said n addressable registers by using multiple positions in the register array (RA) and wherein the old values for the assigned positions of said n addressable registers may be restored up until the time said new positions are assigned a complete of execution status.

Claim 9

The system of Claim 6 further characterized by a back-up register assignment list BRAL connected to said DRAL and which receives and copies the contents of the DRAL upon occurrence of a selected condition and which can copy said contents back into the DRAL upon occurrence of a further selected condition.

Claim 10

The system of Claim 6 further characterized by a plurality of BRAL's each of which independently copies the contents of the DRAL upon occurrence of independent conditions and which can copy said contents back into the DRAL upon occurrence of independent conditions.

Claim 11

The system of Claim 8 characterized in that said ACL has an "ABC" status field for each register containing a status bit for each BRAL to indicate if the contents of the associated register are dependent on a condition which has resulted in the DRAL contents at a selected time being saved in the said BRAL.

Claim 12

A register management system for addressable registers for out of sequence instruction execution characterized by a register array (RA) means of m physical registers in a system architecture requiring that n addressable registers be provided, where m is greater than n, an instruction execution means for executing instructions in said register array (RA) and being connected to send and receive information to said register array (RA), a processor store for holding instructions and data and for providing instructions and data to said instruction execution means, an instruction control means for controlling the movement of instructions from said processor store to said instruction execution means, said instruction control means being connected to said processor store and said instruction execution means, an array control list (ACL) means having m positions where each position is a status identifying field associated with one of the m registers in said register array (RA), said ACL means being connected to receive and send status signals to and from said register array (RA), a decode register assignment list (DRAL) means connected with said register array (RA) for keeping track of instructions, said DRAL means having n positions where each position is a status identifying field associated with the one of the n addressable registers in the system architecture, said DRAL means being connected to receive and send status signals to and from said register array (RA), and logic unit means connected with said array control list means, said decode register assignment list means and said register array means for assigning a physical register equivalent location for each addressable register during instruction execution and where an additional physical register location or locations is assigned equivalent to the same addressable register during execution of an instruction out of order so that both a new value and an old value or values are maintained during out of order instruction execution.

Claim 13

A register management system for addressable registers for out of sequence instruction execution characterized by a register array (RA) means of m physical registers in a system architecture requiring that n addressable registers be provided, where m is greater than n, an instruction execution means for executing instructions in said register array (RA) and being connected to send and receive information to said register array (RA), a processor store for holding instructions and data and for providing instructions and data to said instruction execution means, an instruction control means for controlling the movement of instructions from said processor store to said instruction execution means, said instruction control means being connected to said processor store and said instruction execution means, an array control list (ACL) means having m positions where each position is a status identifying field associated with one of the m registers in said register array (RA), said ACL means being connected to receive and send status signals to and from said register array (RA), a decode register assignment list (DRAL) means connected with said register array (RA) for keeping track of instructions, said DRAL means having n positions where each position is a status identifying field associated with the one of the n addressable registers in the system architecture, said DRAL means being connected to receive and send status signals to and from said register array (RA), and logic unit means connected with said array control list means, said decode register assignment list means and said register array means for assigning a physical register equivalent location for each addressable register during instruction execution and where an additional physical register location or locations is assigned equivalent to the same addressable register during execution of an instruction out of order so that both a new value and an old value or values are maintained during out of order instruction execution.

Claim 14

The system of Claim 10 characterized in that said ACL means and said DRAL means receive instruction status signals and maintain register status information for at least some old values for some of said n addressable registers while out of sequence and conditional branch instructions complete execution and provide new values for assigned positions of said n addressable registers by using multiple positions in the register array (RA) and wherein the old values for the assigned positions of said n addressable registers may be restored up until the time said new positions are assigned a complete of execution status.

Claim 15

The system of Claim 10 further characterized by a back-up register assignment list BRAL connected to said DRAL and which receives and copies the contents of the DRAL upon occurrence of a selected condition and which can copy said contents back into the DRAL upon occurrence of a further selected condition.

Claim 16

The system of Claim 10 further characterized by a plurality of BRAL's each of which independently copies the contents of the DRAL upon occurrence of independent conditions and which can copy said contents back into the DRAL upon occurrence of independent conditions.

Claim 17

The system of Claim 13 characterized in that said ACL has an "ABC" status field for each register containing a status bit for each BRAL to indicate if the contents of the associated register are dependent on a condition which has resulted in the DRAL contents at a selected time being saved in the said BRAL.