Digitally controlled phase locked loop system

Abstract

Abstract In the disclosed embodiment of the invention a phase locked loop system for generating a line-locked clock signal for a television signal processing system includes an analog phase-locked loop (250) nested within a digital phase locked loop (216,218,230,241). The analog phase-locked loop is synchronized to a reference signal (MSB′ sw ) which is derived from the most significant bit of a digital oscillatory signal (SW′) generated by a clocked digital oscillator (230). To reduce instability in this reference signal, the ratio of the frequency of the clock signal (CK′) to the frequency of the digital oscillatory signal (SW′) is chosen to be a noninteger value greater than two. The stability of the reference signal is further enhanced (241) by adaptively delaying (244-248) transitions (236,238) in the reference signal (MSB′ sw ) by amounts of time that are inversely proportional to the value (V sw′ ) of less significant bits of the samples corresponding to the transitions.

Inventors

• 👤 Werner Niklaus Hartmeier

Bibliographic Details