EP0299537A2 — Apparatus and Method for processing digital signal

Claim 1

Independent Claim 151 words

An apparatus for processing a digital signal, comprising: a first RAM (21) which stores a plurality of inputted digital data and a plurality of data of operated result; a second RAM (22) which stores a plurality of constants for implementing a digital filter; a first address pointer (24) which designates an address of said first RAM; a second address pointer (25) which designates an address of said second RAM; a multiplier (27) which multiplies the data being read from said first RAM into the data being read from said second RAM; an ALU (28) which operates a multiplied result from said multiplier with the operated result being stored in an accumulator (29) and makes the accumulator hold operated result thereof; wherein each of said first and second address pointers includes a function for cyclically addressing corresponding one of said first and second RAMs between a predetermined address and a set address.

Claim 2

Independent Claim 151 words

An apparatus for processing a digital signal, comprising: a first RAM (21) which stores a plurality of inputted digital data and a plurality of data of operated result; a second RAM (22) which stores a plurality of constants for implementing a digital filter; a first address pointer (24) which designates an address of said first RAM; a second address pointer (25) which designates an address of said second RAM; a multiplier (27) which multiplies the data being read from said first RAM into the data being read from said second RAM; an ALU (28) which operates a multiplied result from said multiplier with the operated result being stored in an accumulator (29) and makes the accumulator hold operated result thereof; wherein each of said first and second address pointers includes a function for cyclically addressing corresponding one of said first and second RAMs between a predetermined address and a set address.

Claim 3

Independent Claim 192 words

A method for constructing a low-frequency band-pass digital filter, wherein data being stored in a data storage (21) is multiplied into a coefficient being stored in a coefficient storage (22), and a multiplied result thereof is subjected to operation for adding or subtracting in an operation circuit (28), whereby a low-frequency band-pass digital filter of IIR (Infinite Impulse Response) type is constructed, characterized in that said coefficient is divided into the form of α + βδ [wherein α is an integer, δ is a common coefficient (δ<1), and β is a quotient of division of signatures or digits after the decimal point by the common coefficient δ] in advance; that product and sum operation of respective coefficient δ with respect to said data is made; that a result of said product and sum operation is multiplied into said constant β; that product and sum operation of respective coefficient α with respect to said data is made; and that adding or subtracting the multiplied result and the operated result of said product and sum operation of coefficient α with respect to said data is performed to obtain an output of the digital filter.

Claim 4

Independent Claim 192 words

A method for constructing a low-frequency band-pass digital filter, wherein data being stored in a data storage (21) is multiplied into a coefficient being stored in a coefficient storage (22), and a multiplied result thereof is subjected to operation for adding or subtracting in an operation circuit (28), whereby a low-frequency band-pass digital filter of IIR (Infinite Impulse Response) type is constructed, characterized in that said coefficient is divided into the form of α + βδ [wherein α is an integer, δ is a common coefficient (δ<1), and β is a quotient of division of signatures or digits after the decimal point by the common coefficient δ] in advance; that product and sum operation of respective coefficient δ with respect to said data is made; that a result of said product and sum operation is multiplied into said constant β; that product and sum operation of respective coefficient α with respect to said data is made; and that adding or subtracting the multiplied result and the operated result of said product and sum operation of coefficient α with respect to said data is performed to obtain an output of the digital filter.

Claim 5

Independent Claim 202 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means (20) which simultaneously controls operation of said pair of digital processing means in accordance with procedure being programmed in advance characterized in that each of said pair of digital processing means includes storing means (21) for storing address data to cyclically access specific storage areas of an external storage being connected to the outside, operation means (28) for executing operation in which said address data is incremented or decremented and a predetermined value is outputted as an operated result when a incremented or decremented result is a boundary of said specific storage areas in accordance with a single instruction, adding means (28) for adding the operated result from said operation means to a starting address data of said specific storage areas so as to obtain actual address data for said external storage, and that the apparatus further comprises external storage interface means (16) which inputs the actual address data obtained by said adding means through said data buses to said external storage.

Claim 6

Independent Claim 202 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means (20) which simultaneously controls operation of said pair of digital processing means in accordance with procedure being programmed in advance characterized in that each of said pair of digital processing means includes storing means (21) for storing address data to cyclically access specific storage areas of an external storage being connected to the outside, operation means (28) for executing operation in which said address data is incremented or decremented and a predetermined value is outputted as an operated result when a incremented or decremented result is a boundary of said specific storage areas in accordance with a single instruction, adding means (28) for adding the operated result from said operation means to a starting address data of said specific storage areas so as to obtain actual address data for said external storage, and that the apparatus further comprises external storage interface means (16) which inputs the actual address data obtained by said adding means through said data buses to said external storage.

Claim 7

Dependent Claim 64 words

An apparatus in accordance with claim 3, wherein said external storage includes D-RAM (dynamic random access memory), and said external storage interface means includes means (47, 48) for outputting said actual address data such that at least an area other than said specific storage areas can be refreshed while said specific storage areas is cyclically accessed by said actual address data at one time.

Claim 8

Independent Claim 120 words

A method for processing signal, comprising: a first step of executing operation during an execution cycle for a single instruction, wherein address data for accessing specific storage areas of an external storage is read from an internal storage and incremented or decremented, and a predetermined value is outputted as an operated result when an incremented or decremented result is a boundary of said specific storage areas; a second step of transferring a result of said first step to said internal storage; a third step of adding a starting address data of said specific storage areas to a result of said first step; and a fourth step of sending a result of said third step to an external storage interface means.

Claim 9

Independent Claim 120 words

A method for processing signal, comprising: a first step of executing operation during an execution cycle for a single instruction, wherein address data for accessing specific storage areas of an external storage is read from an internal storage and incremented or decremented, and a predetermined value is outputted as an operated result when an incremented or decremented result is a boundary of said specific storage areas; a second step of transferring a result of said first step to said internal storage; a third step of adding a starting address data of said specific storage areas to a result of said first step; and a fourth step of sending a result of said third step to an external storage interface means.

Claim 10

Independent Claim 174 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which for transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means which simultaneously controls operation of said pair of digital processing means in accordance with procedure being programmed in advance characterized in that each of said digital processing means includes storing means (23) for storing a constant "1", a constant "a" being smaller than "1", and a constant "b" being larger than "1", and multiplying means (27) and operation means (28) respectively connected to said storing means and said data buses, and that the apparatus further comprises overflow flag means (56-59) which holds that overflow occurs as a result of said multiplication and operation; and selecting means (26) which selects any one of said constants "1", "a" and "b" based upon a content of said overflow flag means to multiply the selected constant into a coefficient which is multiplied into an inputted digital data.

Claim 11

Independent Claim 174 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which for transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means which simultaneously controls operation of said pair of digital processing means in accordance with procedure being programmed in advance characterized in that each of said digital processing means includes storing means (23) for storing a constant "1", a constant "a" being smaller than "1", and a constant "b" being larger than "1", and multiplying means (27) and operation means (28) respectively connected to said storing means and said data buses, and that the apparatus further comprises overflow flag means (56-59) which holds that overflow occurs as a result of said multiplication and operation; and selecting means (26) which selects any one of said constants "1", "a" and "b" based upon a content of said overflow flag means to multiply the selected constant into a coefficient which is multiplied into an inputted digital data.

Claim 12

Dependent Claim 32 words

An apparatus in accordance with claim 6, further comprising means (20, 34) for resetting said overflow flag means after multiplication of the multiplied result of said coefficient into the inputted digital data.

Claim 13

Dependent Claim 54 words

An apparatus in accordance with claim 6, wherein said inputted digital data includes audio signals of the right channel and the left channel which have been sampled at a predetermined frequency and converted into digital signals, and an input level is adjusted by means of multiplication of said inputted digital data into said coefficient.

Claim 14

Independent Claim 124 words

A method for processing a digital signal, comprising; a first step of multiplying digital data being inputted from the outside into a coefficient, and resetting an overflow flag; a second step of making predetermined multiplication or operation by utilizing a multiplied result of said first step, and setting a maximum value or minimum value as output data when the overflow flag is set in accordance with said predetermined multiplication or operation; a third step of selecting a constant "1", "a" being smaller than "1" or "b" being larger than "1" based upon said overflow flag, and multiplying the same into said coefficient to obtain a new coefficient, whereby a level of the input data is adjusted until no overflow occurs in said second step.

Claim 15

Independent Claim 124 words

A method for processing a digital signal, comprising; a first step of multiplying digital data being inputted from the outside into a coefficient, and resetting an overflow flag; a second step of making predetermined multiplication or operation by utilizing a multiplied result of said first step, and setting a maximum value or minimum value as output data when the overflow flag is set in accordance with said predetermined multiplication or operation; a third step of selecting a constant "1", "a" being smaller than "1" or "b" being larger than "1" based upon said overflow flag, and multiplying the same into said coefficient to obtain a new coefficient, whereby a level of the input data is adjusted until no overflow occurs in said second step.

Claim 16

Dependent Claim 36 words

A method in accordance with claim 9, wherein said digital data is audio signals of the right channel and the left channel which have been sampled at a predetermined frequency and converted into the digital signals.

Claim 17

Independent Claim 171 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which for transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means (20) which simultaneously controls operation of said pair of digital processing means in accordance with procedure being programmed in advance characterized in that the apparatus further comprises interface means (15) including register means (41) which inputs the digital data being applied from the outside in accordance with a control signal being applied from the outside, and holding means (42) which sequentially holds a plurality of the digital data being inputted in said register means and sends said plurality of digital data onto said pair of data buses in accordance with a signal representative of termination of transfer of the data being applied from the outside, and output register means (44) which holds processed data being sent onto said pair of data buses and outputs the processed data to the outside.

Claim 18

Independent Claim 171 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which for transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means (20) which simultaneously controls operation of said pair of digital processing means in accordance with procedure being programmed in advance characterized in that the apparatus further comprises interface means (15) including register means (41) which inputs the digital data being applied from the outside in accordance with a control signal being applied from the outside, and holding means (42) which sequentially holds a plurality of the digital data being inputted in said register means and sends said plurality of digital data onto said pair of data buses in accordance with a signal representative of termination of transfer of the data being applied from the outside, and output register means (44) which holds processed data being sent onto said pair of data buses and outputs the processed data to the outside.

Claim 19

Dependent Claim 146 words

An apparatus in accordance with claim 11, wherein each of said pair of digital processing means includes storing means (21, 22) for storing the data being sent onto the data buses from said interface means, and addressing means (24, 25) for addressing an address of said storing means, and said control means includes a loop counter means (40) for controlling the number of execution times of an instruction for sending the digital data from said holding means of said interface means onto said the pair of data buses, further comprising storage control register means (18) which is connected to one or both of said pair of data buses and controls storing operation of said respective storing means, and the digital data being initially sent from said holding means of said interface means is held in said addressing means, loop counter means and storage control register means.

Claim 20

Dependent Claim 65 words

An apparatus in accordance with claim 12, said pair of digital processing means constructs digital filters which respectively process audio signals of the right channel and the left channel which have been sampled at a predetermined frequency and converted into digital signals, said data which is sent onto said pair of data buses from said interface means includes coefficient data for constructing said digital filters.

Claim 21

Independent Claim 179 words

A method for processing digital signal, comprising: a first step wherein composite data which consists of address data for addressing a pair of storing means for storing digital data, loop data representative of the number of times of operation for transferring said digital data to said pair of storing means, and designating data for designating storing operation of said pair of storing means is fetched from an interface means, and respective data of said composite data are set into addressing means for addressing said pair of storing means, loop counter means provided in control means for controlling transfer of said digital data, and storage control register means for controlling storing operation of respective one of said pair of storing means; and a second step wherein the digital data is fetched from said interface means by the number of times being set in said loop counter means and transferred to said pair of storing means, and the digital data being transferred is stored in said storing means in accordance with a content being set in said storage control register means.

Claim 22

Independent Claim 179 words

A method for processing digital signal, comprising: a first step wherein composite data which consists of address data for addressing a pair of storing means for storing digital data, loop data representative of the number of times of operation for transferring said digital data to said pair of storing means, and designating data for designating storing operation of said pair of storing means is fetched from an interface means, and respective data of said composite data are set into addressing means for addressing said pair of storing means, loop counter means provided in control means for controlling transfer of said digital data, and storage control register means for controlling storing operation of respective one of said pair of storing means; and a second step wherein the digital data is fetched from said interface means by the number of times being set in said loop counter means and transferred to said pair of storing means, and the digital data being transferred is stored in said storing means in accordance with a content being set in said storage control register means.

Claim 23

Dependent Claim 60 words

A method in accordance with claim 14, wherein the digital data which is fetched from said interface means in said second step is coefficient data for constructing a pair of digital filters which process digital data of audio signals of the right channel and the left channel which have been sampled at a predetermined frequency and converted into digital signals.

Claim 24

Independent Claim 95 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means (20) which simultaneously controls operation of said pair of digital processing means in accordance with procedure being programmed in advance characterized in that the apparatus further comprises digital data exchanging means (17) which is provided between said pair of data buses and exchange the digital data on said pair of data buses with each other.

Claim 25

Independent Claim 95 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means (20) which simultaneously controls operation of said pair of digital processing means in accordance with procedure being programmed in advance characterized in that the apparatus further comprises digital data exchanging means (17) which is provided between said pair of data buses and exchange the digital data on said pair of data buses with each other.

Claim 26

Dependent Claim 80 words

An apparatus in accordance with claim 16, wherein said digital data exchanging means includes first register means (17a) which holds the digital data being sent onto one of said data buses and outputs the same onto the other of said data buses, and second register means (17b) which holds the digital data being sent onto the other of said data buses and outputs the same onto one of said data buses, said first and second register means are simultaneously operated.

Claim 27

Independent Claim 174 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means (20) which simultaneously controls said pair of digital processing means in accordance with procedure being programmed in advance characterized in that said control means includes program memory means (32) which stores a program consisting of combination of instruction codes, program counter means (33) which designates an address of said program memory means, decoder means (34) which decodes the instruction codes being fetched from said program memory means and outputs control signal, jump address register means (37, 38) which is connected one or both said pair of data buses and in which an address data of jump address is set, and multiplexer (39) means which selectively applies the address being set in said jump address register means to said program counter means, whereby the address data of the jump address is settable from the outside.

Claim 28

Independent Claim 174 words

An apparatus for processing a digital signal comprises a pair of data buses (11) which transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means (20) which simultaneously controls said pair of digital processing means in accordance with procedure being programmed in advance characterized in that said control means includes program memory means (32) which stores a program consisting of combination of instruction codes, program counter means (33) which designates an address of said program memory means, decoder means (34) which decodes the instruction codes being fetched from said program memory means and outputs control signal, jump address register means (37, 38) which is connected one or both said pair of data buses and in which an address data of jump address is set, and multiplexer (39) means which selectively applies the address being set in said jump address register means to said program counter means, whereby the address data of the jump address is settable from the outside.

Claim 29

Dependent Claim 40 words

An apparatus in accordance with claim 18, wherein said control means includes means (34, JMP) for enabling said jump address register means when a jump instruction is to be executed or when a conditional jump instruction is to be executed.

Claim 30

Independent Claim 162 words

An apparatus for processing a digital data comprises a pair of data buses (11) which transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means which simultaneously controls said pair of digital processing means in accordance with procedure being programmed in advance characterized in that each of said digital processing means including multiplying means (27) and operating means (28), and that the apparatus further comprises conditional jump control means (19) which includes a plurality of pairs of flag means (56-59) which are set when results of said multiplying means and operating means reach a predetermined condition, condition setting register means (55) connected to one or both said pair of data buses, and selecting means (60) for selecting outputs of said plurality of pairs of flag means in accordance with the content of said condition setting register means to output a jump control signal to said control means.

Claim 31

Independent Claim 162 words

An apparatus for processing a digital data comprises a pair of data buses (11) which transfer digital data, a pair of digital processing means (12, 13) which are respectively connected to corresponding one of said data buses, and control means which simultaneously controls said pair of digital processing means in accordance with procedure being programmed in advance characterized in that each of said digital processing means including multiplying means (27) and operating means (28), and that the apparatus further comprises conditional jump control means (19) which includes a plurality of pairs of flag means (56-59) which are set when results of said multiplying means and operating means reach a predetermined condition, condition setting register means (55) connected to one or both said pair of data buses, and selecting means (60) for selecting outputs of said plurality of pairs of flag means in accordance with the content of said condition setting register means to output a jump control signal to said control means.

Claim 32

Dependent Claim 40 words

An apparatus in accordance with claim 20, wherein said plurality of pairs of flag means include a pair of flag means (56-58) which are reset in accordance with a predetermined instruction being executed after execution of a conditional jump instruction.

Claim 33

Dependent Claim 45 words

An apparatus in accordance with claim 21, wherein said plurality of pairs of flag means include a pair of overflow flags (56, 59) which are set when a result of said multiplying means or said operating means exceeds a maximum value or a minimum value.

Apparatus and Method for processing digital signal

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