A byte queing/dequeuing apparatus for handling variable-length data words/instructions in a single clock cycle

Claim 1

A byte queuing/dequeuing apparatus for handling variable-length data words/instructions in a single clock cycle comprising: an input data bus; means for placing successive sets of a predetermined number of bytes of data on said input data bus; an output data bus; a plurality of FIFO's equal in number to said predetermined number of bytes, each of said FIFO's being capable of handling one of said predetermined number of bytes at any one time; an input rotator coupled between said input data bus and said FIFO's; an output rotator coupled between said FIFO's and said output data bus; means responsive to the number of said bytes previously queued in said FIFO's for generating a control signal to said input rotator for rotating the bytes received by said input rotator from said input data bus according to the formula X MOD A = y where X = number of bytes previously queued in said FIFO's A = number of FIFO's in said apparatus y = number of places the bytes in said input rotator are rotated in a first direction before being stored in said FIFO's means responsive to a control signal corresponding to the number of bytes currently being queued for enabling the next available FIFO's as required for storing said predetermined number of bytes; means responsive to the number of said bytes previously dequeued from said FIFO's for generating a control signal to said output rotator for rotating the bytes received by said output rotator from said FIFO's according to the formula W MOD A = Z where W = number of bytes previously dequeued from said FIFO's A = number of FIFO's in said apparatus Z = number of places the bytes in said output rotator are rotated in a second direction before being placed on said output data bus; and means responsive to a control signal corresponding to the number of bytes currently being dequeued for pointing to the next FIFO's having bytes available to be dequeued.

Claim 7

A method of handling variable-length data words/instructions in an apparatus having an input data bus, an output data bus, an input rotator, an output rotator and a plurality of FIFO's, comprising the steps of: placing successive sets of a predetermined number of bytes of data on said input data bus; transferring said predetermined number of bytes from said input data bus to said input rotator for storage in said FIFO's; rotating the bytes received by said input rotator from said input data bus according to the formula X MOD A = y where X = number of bytes previously queued in said FIFO's A = number of FIFO's in said apparatus y = number of places the bytes in said input rotator are rotated in a first direction before being stored in said FIFO's generating a control signal corresponding to the number of bytes currently being queued; enabling the next available FIFO's as required for storing said bytes currently being queued; transferring said predetermined number of bytes from said FIFO's to said output rotator; generating a control signal to said output rotator for rotating the bytes received by said output rotator from said FIFO's according to the formula W MOD A = Z where W = number of bytes previously dequeued from said FIFO's A = number of FIFO's in said apparatus Z = number of places the bytes in said output rotator are rotated in a second direction before being placed on said output data bus; generating a control signal corresponding to the number of bytes currently being dequeued; and pointing to the FIFO's next in order having bytes available to be dequeued.

Claim 8

A method of handling variable-length data words/instructions in an apparatus having an input data bus, an output data bus, an input rotator, an output rotator and a plurality of FIFO's, comprising the steps of: placing successive sets of a predetermined number of bytes of data on said input data bus; transferring said predetermined number of bytes from said input data bus to said input rotator for storage in said FIFO's; rotating the bytes received by said input rotator from said input data bus according to the formula X MOD A = y where X = number of bytes previously queued in said FIFO's A = number of FIFO's in said apparatus y = number of places the bytes in said input rotator are rotated in a first direction before being stored in said FIFO's generating a control signal corresponding to the number of bytes currently being queued; enabling the next available FIFO's as required for storing said bytes currently being queued; transferring said predetermined number of bytes from said FIFO's to said output rotator; generating a control signal to said output rotator for rotating the bytes received by said output rotator from said FIFO's according to the formula W MOD A = Z where W = number of bytes previously dequeued from said FIFO's A = number of FIFO's in said apparatus Z = number of places the bytes in said output rotator are rotated in a second direction before being placed on said output data bus; generating a control signal corresponding to the number of bytes currently being dequeued; and pointing to the FIFO's next in order having bytes available to be dequeued.