Patent EP0298255B1 successfully refreshed from Google Patents.
EP0298255B1
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Circuit for driving a liquid crystal display panel
Assignee: Seiko Epson Corp
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Filing: 1988-06-01
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Granted: 1992-12-02
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Expires: 2008-06-01
Abstract
No abstract record available.
Inventors
- 👤 Masahide Uchida
- 👤 Fumio Shida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 18:22
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/2007; G09G3/2011; G09G3/34; G09G3/36; G09G3/3611; G09G3/3648; G09G3/3666; G09G3/3685; G09G3/3688; H; H04; H04N; H04N3/00; H04N3/10; H04N3/12; H04N3/127; H04N9/00; H04N9/12; H04N9/31; H04N9/3141; H04N9/3147; G09G2310/00; G09G2310/02; G09G2310/0243; G09G2310/0248; G09G2310/0264; G09G2310/027
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
214 words
A circuit for driving a matrix display device having M rows and N columns by video digital input data consisting of K bits wherein K is an integer at least equal to one, the columns intersecting the rows, a pixel being formed at each intersection of a row and a column said circuit comprising: analogue switching means (28; 28') capable of an ON and an OFF state for receiving a control voltage (Vcont) and a control signal and selectively outputting the control voltage to each row, wherein the control voltage varies in level at least between an OFF state of the liquid crystal display and an ON state at least once each horizontal scanning period; and control means (21-26) for receiving the K bit digital input data and producing the control signal for controlling the time of commencement of the ON state of the analogue switching means (28; 28') in response to said input data, characterized in that said circuit is for driving an active matrix liquid crystal display having a thin film transistor (17) as part of each pixel, that said control voltage varies continuously in level and that said control means (21-26) produces said control signal for controlling the time period of the ON state of the analog switching means (28; 28').
Claim 2
Dependent Claim
144 words
The circuit of claim 1, wherein the control means comprises a shift register means (21) for providing a shifted output, at least a portion of the shifted outputs each being associated with a pixel along a row during each horizontal scanning period; a plurality of latching means (22, 29; 23, 30) each associated with one of the pixels along a row during each horizontal scanning period for receiving the K bit digital data to provide a latched data signal; binary counter means (24) for producing a gray scale reference signal variable in a range substantially corresponding to the range of the K bit digital input data during each cycle of the control voltage; and a plurality of comparator means (25, 38) each associated with a latching means for comparing the latched data signal and the gray scale reference signal to produce the control signal.
Claim 3
Dependent Claim
114 words
The circuit of claim 2, wherein each of said plurality of latching means includes a first latching means (22, 29) for receiving the K bit digital data and latching the input in response to a shifted output of the shift register means (21) to provide a first latched data signal; and a plurality of second latching means (23, 30), each for receiving a common latch clock signal (LCL) and the associated first latched data signal for essentially simultaneously latching all of the first latched data signals of the first latching means to produce in each of the corresponding second latching means a second latched data signal for application to the comparator means (25, 38).
Claim 4
Dependent Claim
45 words
The circuit of claim 2 or 3, wherein the analogue switching means includes an analogue switch (28) associated with each said pixel along a row for applying a control voltage to the associated pixel of a level determined by the K bit digital input data.
Claim 5
Dependent Claim
47 words
The circuit of claim 2, and including a pluraltiy of flip flop storage means (26) each associated with a comparator means (38) for storing the output of the comparator means at least during each cycle of the control voltage for application to the analogue switching means (28).
Claim 6
Dependent Claim
32 words
The circuit of claim 5, and including level shifter means (27) for increasing the level of each of the flip flop storage means (26) for application to the analogue switching means (28).
Claim 7
Dependent Claim
40 words
The circuit of claim 3, wherein each of the first and second latching means (22; 23) includes K flip flops (29; 30) which are commonly clocked, one of said flip flops being associated with each of the K data bits.
Claim 8
Dependent Claim
86 words
The circuit of claim 1 or 2, wherein the analogue switching means (28') comprises discharging switch means (SWD) for receiving a discharging signal and a discharge power supply input and for selectively applying the discharge power supply input in reponse to the discharging signal to the associated column before the application of the control voltage to the column; and a charging switch (SWV) for receiving the control voltage in response to the control signal, said control voltage having a higher impedance than the discharge power supply.
Claim 9
Dependent Claim
32 words
The circuit of claim 8, further comprising third latching means (51-53) for receiving the output of the analogue switching means (28, 28') and latching the signal until the following horizontal scanning period.
Claim 10
Dependent Claim
75 words
The circuit of claim 9, wherein the third latching means includes a first step sample hold circuit (51) for receiving the output of the analogue switching means (28, 28') and producing a latched sample signal; a second analogue switching means (52) for receiving the latched sample signal and a second step sample hold circuit (53) for receiving the output ON from the second analogue switch for latching the output until the following horizontal scanning period.
Claim 11
Dependent Claim
25 words
The circuit of claim 10, and including analogue buffer means (54) between the second step sample hold circuit (53) and the associated column of pixels.
Claim 12
Dependent Claim
25 words
The circuit of claim 10, wherein the first and second step sample hold circuits (51, 53) each comprise a capacitor coupled to a reference voltage.
Claim 13
Dependent Claim
11 words
The circuit of claim 12, wherein the reference voltage is ground.
Claim 14
Dependent Claim
34 words
The circuit of any of claims 1 to 13, wherein the control voltage (Vcont) varies in level by increasing from an OFF state of the liquid crystal display to at least an ON state.
Claim 15
Dependent Claim
170 words
A circuit for driving an active-matrix liquid crystal display panel (3) comprising M source lines (15), N gate lines (16), N x M pixels at the crossing points of the source and gate lines, each pixel comprising a thin film transistor (17) having its gate and source connected to the crossing gate and source lines, respectively and having its drain connected to a control electrode of a liquid crystal element (18), a first input for receiving a K bit digital input signal, a second input for receiving a saw-tooth like periodic control voltage the value of which increases during one period from a first level corresponding to the OFF condition of the liquid crystal elements to a second value corresponding to the ON condition of the liquid crystal elements, analogue switches (28; 28'; SWV, SWD) for connecting and disconnecting the second input with the source lines (15), and control means (21-27) for controlling the duration of the ON state of the analogue switches in accordance with the digital input signal.
Claim 16
Dependent Claim
57 words
A circuit according to claim 15, wherein said control means includes M sample-and-hold circuits (22, 23) for sampling and holding the digital input signal and a signal converter (25, 26) for converting each sampled value of the digital input signal into a corresponding time duration for controlling the duration of the ON state of said analogue switches.
References Cited (Backward Citations)
No citation records indexed.
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