Field effect transistor with short channel length and process of fabrication thereof

Claim 2

A field effect transistor fabricated on a semiconductor substrate of a first conductivity type and comprising an insulating film form on said semiconductor substrate, a semiconductor layer of said first conductivity type formed in said insulating layer, said semiconductor layer being in contact with said semiconductor substrate, an insulating film covering a side surface of said semiconductor layer, a part of said insulating film providing a gate insulating film, a gate electrode formed in said insulating film and contacting to said gate insulating film, and source and drain regions of a second conductivity type formed in said insulating film characterized in that said semiconductor layer has relatively long protrusions and a relatively short protrusion located between the relatively long protrusion, respective leading edges of said relatively long protrusions being in contact with said source and drain regions, respectively, said relatively short protrusion being in contact with a central portion of said gate insulating film.

Claim 3

A field effect transistor as set forth in claim 1, in which said gate electrode has a length of submicron.

Claim 4

A field effect transistor as set forth in claim 2, in which said semiconductor substrate is formed of a p-type single crystal silicon.

Claim 5

A field effect transistor as set forth in claim 3, in which said insulating film is formed of a silicon oxide.

Claim 6

A field effect transistor as set forth in claim 4, in which said semiconductor layer is formed of an epitaxial silicon.

Claim 7

A field effect transistor as set forth in claim 5, in which said gate insulating film is formed of a silicon oxide.

Claim 8

A field effect transistor as set forth in claim 6, in which said gate electrode is formed of a heavily doped n-type polysilicon.

Claim 9

A field effect transistor as set forth in claim 7, in which said source and drain regions are formed of a heavily doped n-­type silicon.

Claim 10

A field effect transistor as set forth in claim 8, in which each of said source and drain regions has a thickness of about 0.3 micron and an impurity atom concentration of about 2 x 10²⁰ atoms/cm³.

Claim 11

A process of fabricating a field effect transistor, characterized by the steps of: a) preparing a semiconductor substrate of a first conductivity type having an upper surface; b) forming a first insulating film on the upper surface of said semiconductor substrate, said first insulating film having an upper surface; c) forming a first cavity in said first insulating film, said first cavity being open at one end thereof to the upper surface of said semiconductor substrate and at the other end thereof to the upper surface of said first insulating film; d) filling said first cavity with a semiconductor material of said first conductivity type having an upper surface; e) covering a part of the upper surface of said semiconductor material with a first mask; f) forming a second mask on the upper surface of said semiconductor material, said second mask being located in the neighborhood of said first mask ; g) doping said semiconductor material with impurity atoms of a second conductivity type opposite to said first conductivity type using said first and second masks for preventing a part of said semiconductor material covered with said first and second masks from said impurity atoms, thereby forming an impurity region of said second conductivity type; h) removing said second mask; i) forming a second cavity partially in said impurity region and partially in said semiconductor material; j) forming a second insulating film covering edge surfaces of said semiconductor material and said impurity region, said edge surfaces defining said second cavity, a part of said second insulating film covering the edge surface of said semiconductor material providing a gate insulating film; and k) forming a gate electrode in said second cavity.

Claim 12

A process of fabricating a field effect transistor, characterized by the steps of: a) preparing a semiconductor substrate of a first conductivity type having an upper surface; b) forming a first insulating film on the upper surface of said semiconductor substrate, said first insulating film having an upper surface; c) forming a first cavity in said first insulating film, said first cavity being open at one end thereof to the upper surface of said semiconductor substrate and at the other end thereof to the upper surface of said first insulating film; d) filling said first cavity with a semiconductor material of said first conductivity type having an upper surface; e) covering a part of the upper surface of said semiconductor material with a first mask; f) forming a second mask on the upper surface of said semiconductor material, said second mask being located in the neighborhood of said first mask ; g) doping said semiconductor material with impurity atoms of a second conductivity type opposite to said first conductivity type using said first and second masks for preventing a part of said semiconductor material covered with said first and second masks from said impurity atoms, thereby forming an impurity region of said second conductivity type; h) removing said second mask; i) forming a second cavity partially in said impurity region and partially in said semiconductor material; j) forming a second insulating film covering edge surfaces of said semiconductor material and said impurity region, said edge surfaces defining said second cavity, a part of said second insulating film covering the edge surface of said semiconductor material providing a gate insulating film; and k) forming a gate electrode in said second cavity.

Claim 13

A process of fabricating a field effect transistor as set forth in claim 10, in which said first cavity has a generally inverted L-shaped configuration.

Claim 14

A process of fabricating a field effect transistor as set forth in claim 10, in which said first mask is formed by a deposition of an insulating material followed by an etching thereof.

Claim 15

A process of fabricating a field effect transistor as set forth in claim 12, in which said insulating material is of a silicon oxide.

Claim 16

A process of fabricating a field effect transistor as set forth in claim 13, in which said second mask is formed by a formation of an etching stopper film structure on the upper surface of said semiconductor material and a deposition of an insulating material followed by an anisotropic etching thereof.

Claim 17

A process of fabricating a field effect transistor as set forth in claim 14, in which said etching stopper film structure is provided with a silicon oxide film and a polysilicon film.

Claim 18

A process of fabricating a field effect transistor as set forth in claim 14, in which said insulating material is of a silicon oxide.

Claim 19

A process of fabricating a field effect transistor as set forth in claim 14, in which said anisotropic etching is carried out by using a reactive ion etching technique.

Claim 20

A process of fabricating a field effect transistor as set forth in claim 10, in which said impurity atoms are implanted into said semiconductor material.

Claim 21

A process of fabricating a field effect transistor as set forth in claim 10, in which said second cavity is formed by a reactive ion etching technique.

Claim 22

A process of fabricating a field effect transistor as set forth in claim 10, in which said gate electrode is formed by a deposition of a conductive material followed by a pattering thereof.

Claim 23

A process of fabricating a field effect transistor as set forth in claim 20, in which said conductive material is of a doped polysilicon.