Memory capacity detection apparatus

Claim 2

A memory capacity detection apparatus for detecting a capacity of one RAM (1) of a plurality of RAMs each of which is constituted by 2 N blocks each having a predetermined memory capacity, and to which an address signal representing an existing memory capacity is fed, comprising: address control means (2) for designating a prede­termined address in each block of said RAM (1); code write means (3) for sequentially writing a detection code at the predetermined address in each block of said RAM (1); code readout means (4) for reading out the detec­tion code from the predetermined address of a first block of the RAM (1) designated by said address control means (2); and code comparison means (5) for sequentially compar­ing the detection code read out by said code readout means (4) and the detection code written by said code write means (3) so as to detect a coincidence therebe­tween, thereby detecting the capacity of said RAM (1).

Claim 3

A memory capacity detection apparatus for detecting a capacity of one RAM (1) of a plurality of RAMs each of which is constituted by 2 N blocks each having a predetermined memory capacity, and to which an address signal representing an existing memory capacity is fed, comprising: address control means (2) for designating a prede­termined address in each block of said RAM (1); code write means (3) for sequentially writing a detection code at the predetermined address in each block of said RAM (1); code readout means (4) for reading out the detec­tion code from the predetermined address of a first block of said RAM (1) designated by said address control means (2); code comparison means (5) for sequentially compar­ing the detection code read out by said code readout means (4) and the detection code written by said code write means (3) so as to detect a coincidence therebe­ween, thereby detecting the capacity of said RAM (1); and code/address control means (6) for outputting a control signal for reading out the detection code stored at the predetermined address in said first block of said RAM (1).

Claim 4

A memory capacity detection apparatus for detecting a capacity of one RAM (1) of a plurality of RAMs each of which is constituted by 2 N blocks each having a predetermined memory capacity, and to which an address signal representing an existing memory capacity is fed, comprising: address control means (2) for designating a prede­termined address in each block of said RAM (1); code write means (3) for sequentially writing a detection code at the predetermined address in each block of said RAM (1); code readout means (4) for reading out the detec­tion code from the predetermined address of a first block of said RAM (1) designated by said address control means (2); code comparison means (5) for sequentially compar­ing the detection code read out by said code readout means (4) and the detection code written by said code write means (3) so as to detect a coincidence therebe­ween, thereby detecting the capacity of said RAM (1); and code/address control means (6) for outputting a control signal for reading out the detection code stored at the predetermined address in said first block of said RAM (1).

Claim 5

A memory capacity detection apparatus for detecting a capacity of one RAM (1) of a plurality of RAMs each of which is constituted by 2 N blocks each having a predetermined memory capacity, and to which an address signal representing an existing memory capacity is fed, comprising: address control means (2) for designating a prede­termined address in each block of said RAM (1); code write means (3) for sequentially writing a detection code at the predetermined address in each block of said RAM (1); code readout means (4) for reading out the detec­tion code from the predetermined address of a first block of said RAM (1) designated by said address control means (2); code comparison means (5) for sequentially com­paring the detection code read out by said code readout means (4) and the detection code written by said code write means (3) so as to detect a coincidence therebe­tween, thereby detecting the capacity of said RAM (1); code/address control means (6) for, when the two detection codes compared by said code comparison means (5) do not coincide with each other, outputting a control signal for causing said address control means (6) to generate the predetermined address for accessing a next block of said RAM (1), causing said code write means (3) to output a detection code and to write the detection code, and causing said code readout means (4) to read out the detection code stored at the predeter­mined address in said first block of said RAM (1); and memory capacity storage means (7) for storing a capacity of said RAM detected based on the output from said code comparison means (5).

Claim 6

A memory capacity detection apparatus for detecting a capacity of one RAM (1) of a plurality of RAMs each of which is constituted by 2 N blocks each having a predetermined memory capacity, and to which an address signal representing an existing memory capacity is fed, comprising: address control means (2) for designating a prede­termined address in each block of said RAM (1); code write means (3) for sequentially writing a detection code at the predetermined address in each block of said RAM (1); code readout means (4) for reading out the detec­tion code from the predetermined address of a first block of said RAM (1) designated by said address control means (2); code comparison means (5) for sequentially com­paring the detection code read out by said code readout means (4) and the detection code written by said code write means (3) so as to detect a coincidence therebe­tween, thereby detecting the capacity of said RAM (1); code/address control means (6) for, when the two detection codes compared by said code comparison means (5) do not coincide with each other, outputting a control signal for causing said address control means (6) to generate the predetermined address for accessing a next block of said RAM (1), causing said code write means (3) to output a detection code and to write the detection code, and causing said code readout means (4) to read out the detection code stored at the predeter­mined address in said first block of said RAM (1); and memory capacity storage means (7) for storing a capacity of said RAM detected based on the output from said code comparison means (5).

Claim 10

An electronic applied measuring equipment comprising: a measuring equipment body (100); and RAM capacity detecting means, provided to said measuring equipment body, for detecting a capacity of a RAM (1) storing data required for measurement procedures and/or processes by said measuring equipment body, said RAM (1) is one of a plurality of RAMs each of which is constituted by 2 N blocks each having a prede­termined memory capacity, and to which an address signal representing an existing memory capacity is fed, and said RAM capacity detecting means comprising: address control means for designating a predeter­mined address in each block of said RAM (1); code write means for sequentially writing a detec­tion code at the predetermined address in each block of said RAM (1); code readout means for reading out the detection code from the predetermined address of a first block of said RAM (1) designated by said address control means; and code comparison means for sequentially comparing the detection code read out by said code readout means and the detection code written by said code write means so as to detect a coincidence therebetween, thereby detecting the capacity of said RAM (1).

Claim 11

An electronic applied measuring equipment comprising: a measuring equipment body (100); and RAM capacity detecting means, provided to said measuring equipment body, for detecting a capacity of a RAM (1) storing data required for measurement procedures and/or processes by said measuring equipment body, said RAM (1) is one of a plurality of RAMs each of which is constituted by 2 N blocks each having a prede­termined memory capacity, and to which an address signal representing an existing memory capacity is fed, and said RAM capacity detecting means comprising: address control means for designating a predeter­mined address in each block of said RAM (1); code write means for sequentially writing a detec­tion code at the predetermined address in each block of said RAM (1); code readout means for reading out the detection code from the predetermined address of a first block of said RAM (1) designated by said address control means; and code comparison means for sequentially comparing the detection code read out by said code readout means and the detection code written by said code write means so as to detect a coincidence therebetween, thereby detecting the capacity of said RAM (1).