Patent EP0289274A2 successfully refreshed from Google Patents.
EP0289274A2
Expired / Lapsed
EP
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Via connections in integrated circuits
Assignee: HP Inc
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Filing: 1988-04-27
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Granted: —
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Expires: 2008-04-27
Abstract
Abstract A via connection and method for making the same for integrated circuits having multiple layers of electrically conductive interconnect lines (16,18) separated by an insulative layer (32). The via connection has a very thin layer (36) of relatively high resistivity material lining the via hole (30) in conductive contact with interconnect lines in two layers. The resistivity of the thin layer material is in a range from about 10 to about 50 times the interconnect line resistivities and generally has a thickness of less than 100 nanometers. The thin layer assures more uniform current flow in the via connection thereby preventing electromigration, with reduced peak local current density by causing current to swing more widely around the corner at the interface between the interconnect lines at the via.
Inventors
- 👤 Yoshio Nishi
- 👤 Keunmyung Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 17:13
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
82 words
An integrated circuit having first and second electrical conductors (16,18) respectively at two levels separated by an insulating layer (32) with a via connection (30) between said first and second conductors, wherein the via connection is formed by an integral extension (34) of the first conductor (18) through an aperture in the insulating layer, characterized by a relatively thin conductive layer (38) of a material of resistivity relatively higher than that of the conductors between said integral extension and the second conductor.
Claim 2
Dependent Claim
82 words
An integrated circuit having first and second electrical conductors (16,18) respectively at two levels separated by an insulating layer (32) with a via connection (30) between said first and second conductors, wherein the via connection is formed by an integral extension (34) of the first conductor (18) through an aperture in the insulating layer, characterized by a relatively thin conductive layer (38) of a material of resistivity relatively higher than that of the conductors between said integral extension and the second conductor.
Claim 3
Dependent Claim
149 words
An integrated circuit having a plurality of layers of electrically conductive lines (16,18) separated by insulative material (32) and a via connection, comprising; a first electrically conductive line (16) on a first level, said first line having a first line resistivity, a layer (32) of insulative material disposed over said first level, said layer of insulative material having a hole (30) formed therein over said first line, a thin electrically conductive layer (36) disposed in said hole in contact with said first line, said thin layer having a resistivity in a range from about 10 to about 50 times said first line resistivity, and a second electrically conductive line (18) on a second level disposed over said layer of insulative material, said second line extending into said hole in contact with said thin layer, said second line having a second line resistivity approximately equal to said first line resistivity.
Claim 4
Dependent Claim
149 words
An integrated circuit having a plurality of layers of electrically conductive lines (16,18) separated by insulative material (32) and a via connection, comprising; a first electrically conductive line (16) on a first level, said first line having a first line resistivity, a layer (32) of insulative material disposed over said first level, said layer of insulative material having a hole (30) formed therein over said first line, a thin electrically conductive layer (36) disposed in said hole in contact with said first line, said thin layer having a resistivity in a range from about 10 to about 50 times said first line resistivity, and a second electrically conductive line (18) on a second level disposed over said layer of insulative material, said second line extending into said hole in contact with said thin layer, said second line having a second line resistivity approximately equal to said first line resistivity.
Claim 5
Dependent Claim
27 words
The integrated circuit of claim 1 or 2, wherein said thin conductive layer has a thickness in a range from about 0.05 um to about 0.1 um.
Claim 6
Dependent Claim
26 words
The integrated circuit of claim 1,2 or 3 wherein said hole formed in said layer of insulative material has a diameter of less than 1.0 um.
Claim 7
Dependent Claim
20 words
The integrated circuit of 2,3 or 4 wherein said thin layer lines both the bottom and sides of said hole.
Claim 8
Dependent Claim
20 words
The integrated circuit of 2,3 or 4 wherein said thin layer lines both the bottom and sides of said hole.
Claim 9
Dependent Claim
20 words
The integrated circuit of any preceding claim wherein said first and second lines are either of aluminium or of gold.
Claim 10
Dependent Claim
42 words
The integrated circuit of any preceding claim wherein said thin layer is composed of electrically resistive metallic material selected from the group consisting of lead and alloys containing at least two of nickel, chromium, iron, copper, manganese, tungsten and silicides of these.
Claim 11
Independent Claim
147 words
A method of forming via connections in an integrated circuit comprising, forming a first level of first electrically conductive lines (16) connected to individual circuit elements on a semiconductor chip, applying a layer (32) of insulative material on said first level, creating a plurality of holes (30) in said layer of insulative material, said holes being formed over and exposing portions of said first electrically conductive lines (16), depositing a thin layer (36) of eclectrically conductive material in said holes so as to contact said first conductive lines, said thin layer having a resistivity relatively higher than the resistivity of said first conductive lines, and forming a second level of second electrically conductive lines (18), said second lines extending into said holes (30) into contact with said thin layer (36), said second lines having a resistivity which is approximately equal to said resistivity of said first lines.
Claim 12
Independent Claim
147 words
A method of forming via connections in an integrated circuit comprising, forming a first level of first electrically conductive lines (16) connected to individual circuit elements on a semiconductor chip, applying a layer (32) of insulative material on said first level, creating a plurality of holes (30) in said layer of insulative material, said holes being formed over and exposing portions of said first electrically conductive lines (16), depositing a thin layer (36) of eclectrically conductive material in said holes so as to contact said first conductive lines, said thin layer having a resistivity relatively higher than the resistivity of said first conductive lines, and forming a second level of second electrically conductive lines (18), said second lines extending into said holes (30) into contact with said thin layer (36), said second lines having a resistivity which is approximately equal to said resistivity of said first lines.
Claim 13
Dependent Claim
24 words
A method as in claim 8 wherein the thin layer has a resistivity between 10 and 50 times that of the first conductive lines.
Claim 14
Dependent Claim
59 words
The method of claim 8 or 9 wherein said holes are formed in said layer of insulative material by applying a resist layer to said layer of insulative material, patterning hole areas in said resist with a mask, removing said hole areas, and etching said layer of insulative material where said hole areas of said resist have been removed.
Claim 15
Independent Claim
180 words
A method of forming via connections in integrated circuit wafers comprising, forming a first metal layer of first electrically conductive lines connected to individual circuit elements on a patterned semiconductor wafer having a first insulative layer thereover, said first lines characterized by a line resistivity, applying a second layer of insulative material over said first metal layer, patterning a plurality of via holes in said second insulative layer, said via holes being located above and exposing selected portions of said first lines, applying a thin layer of electrically resistive material over said layer of insulative material, said thin layer extending into and lining the bottom of said via holes and contacting said exposed selected portions of said first lines, the thin layer characterized by a resistivity in a range from about 10 to about 50 times said line resistivity, and forming a second metal layer of second electrically conductive lines said second lines extending into said holes into contact with said thin layer, said second lines characterized by a resistivity approximately equal to said line resistivity of said first lines.
Claim 16
Independent Claim
180 words
A method of forming via connections in integrated circuit wafers comprising, forming a first metal layer of first electrically conductive lines connected to individual circuit elements on a patterned semiconductor wafer having a first insulative layer thereover, said first lines characterized by a line resistivity, applying a second layer of insulative material over said first metal layer, patterning a plurality of via holes in said second insulative layer, said via holes being located above and exposing selected portions of said first lines, applying a thin layer of electrically resistive material over said layer of insulative material, said thin layer extending into and lining the bottom of said via holes and contacting said exposed selected portions of said first lines, the thin layer characterized by a resistivity in a range from about 10 to about 50 times said line resistivity, and forming a second metal layer of second electrically conductive lines said second lines extending into said holes into contact with said thin layer, said second lines characterized by a resistivity approximately equal to said line resistivity of said first lines.
References Cited (Backward Citations)
No citation records indexed.
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