A multi-level integrated circuit wiring structure from a single metal deposit

Claim 2

A metallization structure formed on an insulation layer on a processed semiconductor substrate, comprising: at least one stud-down; a plurality of interconnection lines, at least one of said plurality of interconnection lines having a first thickness and at least another one of said plurality of interconnection lines having a second thickness greater than said first thickness; and at least one stud-up, said stud-down, said plurality of interconnection lines and said stud-up being formed from a single layer of metal.

Claim 3

A process for forming a multi-level metallization structure on a processed semiconductor substrate, comprising the steps of: forming a planar insulating layer on said processed semiconductor substrate; masking and etching said planar insulating layer to form a plurality of wiring troughs in an upper portion of said insulating layer and at least one stud-down via in a lower portion of said insulating layer; depositing a layer of metal to fill both of said at least one stud-down via and said plurality of wiring troughs, and to form a coating of a thickness X on top of said planar insulating layer; masking and etching said layer of metal to define at least one stud-up as well as a plurality of interconnec­tion lines, at least one of said plurality of said interconnection lines being defined by said layer of metal within one of said plurality of wiring troughs and by a portion of said layer of metal said portion being of a thickness less than X and at least another one of said plurality of interconnecting lines being defined solely by said layer of metal within one of said plurality of wiring troughs; so that said stud-down, said plurality of interconnec­tion lines, and said stud-up are all formed from a single layer of metal.

Claim 4

A process for forming a multi-level metallization structure on a processed semiconductor substrate, comprising the steps of: forming a planar insulating layer on said processed semiconductor substrate; masking and etching said planar insulating layer to form a plurality of wiring troughs in an upper portion of said insulating layer and at least one stud-down via in a lower portion of said insulating layer; depositing a layer of metal to fill both of said at least one stud-down via and said plurality of wiring troughs, and to form a coating of a thickness X on top of said planar insulating layer; masking and etching said layer of metal to define at least one stud-up as well as a plurality of interconnec­tion lines, at least one of said plurality of said interconnection lines being defined by said layer of metal within one of said plurality of wiring troughs and by a portion of said layer of metal said portion being of a thickness less than X and at least another one of said plurality of interconnecting lines being defined solely by said layer of metal within one of said plurality of wiring troughs; so that said stud-down, said plurality of interconnec­tion lines, and said stud-up are all formed from a single layer of metal.

Claim 5

A process for forming a multi-level wiring structure on a processed semiconductor substrate, comprising: forming an insulating layer on said processed semicon­ductor substrate; masking and etching said insulating layer to define a plurality of wiring troughs; further masking and etching said insulating layer to define at least one stud-down via in a lower portion of at least one of said wiring troughs; depositing a layer of conductive material to fill each said stud-down via and said plurality of wiring troughs, and to form a layer of conductive material of a predetermined thickness on top of said insulating layer; masking and etching said conductive layer to form at least one stud-up structure; and further masking and etching said conductive layer to form a plurality of thick and thin interconnection lines, said thick interconnection lines being defined by the conductive material within a wiring trough and some of the conductive material above the trough, said thin interconnection lines being defined by either the conductive material solely within a wiring trough or a thickness of said conductive material not lying above a wiring trough; so that said stud-down, said stud-up, said thick interconnection lines and said thin interconnection lines are formed from the same deposit of conductive material.

Claim 6

A process for forming a multi-level wiring structure on a processed semiconductor substrate, comprising: forming an insulating layer on said processed semicon­ductor substrate; masking and etching said insulating layer to define a plurality of wiring troughs; further masking and etching said insulating layer to define at least one stud-down via in a lower portion of at least one of said wiring troughs; depositing a layer of conductive material to fill each said stud-down via and said plurality of wiring troughs, and to form a layer of conductive material of a predetermined thickness on top of said insulating layer; masking and etching said conductive layer to form at least one stud-up structure; and further masking and etching said conductive layer to form a plurality of thick and thin interconnection lines, said thick interconnection lines being defined by the conductive material within a wiring trough and some of the conductive material above the trough, said thin interconnection lines being defined by either the conductive material solely within a wiring trough or a thickness of said conductive material not lying above a wiring trough; so that said stud-down, said stud-up, said thick interconnection lines and said thin interconnection lines are formed from the same deposit of conductive material.