Patent EP0286988A2 successfully refreshed from Google Patents.
EP0286988A2
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EP
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Method and apparatus for testing missile systems
Assignee: Raytheon Co
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Filing: 1988-04-08
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Granted: —
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Expires: 2008-04-08
Abstract
Abstract A method and apparatus for testing missile software is disclosed. The apparatus (10) comprises a missile data processor interface circuit (14) for interfacing the data processor (16) of the missile with the apparatus (10). The apparatus (10) further comprises a circuit (18) for real-time collection of information appearing on at least one of the memory buses of the missile data processor. The circuit (18) for real-time collection of data is in electrical communication with the data processor interface circuit (14) and a computer (24).
Inventors
- 👤 Jeffrey Lowenson
- 👤 Khosrow Hessamian
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; F; F41; F41G; F41G7/00; F41G7/006; G06F11/22; G06F11/2273
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
82 words
An apparatus for testing missile systems. said apparatus electrically communicating with a computer and with a data processor of a missile having a plurality of memory buses. said apparatus comprising: data processor interface buffer means for interfacing said data processor of said missile with said apparatus: and means for real-time collection of data appearing on at least one of said memory buses. said means for real-time collection of data electrically communicating with said computer and with said data processor interface buffer means.
Claim 2
Independent Claim
82 words
An apparatus for testing missile systems. said apparatus electrically communicating with a computer and with a data processor of a missile having a plurality of memory buses. said apparatus comprising: data processor interface buffer means for interfacing said data processor of said missile with said apparatus: and means for real-time collection of data appearing on at least one of said memory buses. said means for real-time collection of data electrically communicating with said computer and with said data processor interface buffer means.
Claim 3
Dependent Claim
38 words
The apparatus in Claim 1, wherein said means for real-time collection of data is operable to cause said computer to pause when the information appearing on at least ore of said memory buses is of a predetermined value.
Claim 4
Dependent Claim
37 words
The apparatus of Claim 1, wherein said means for real-time collection of data is operable to count the number of occurrences that information appearing on at least one of said memory buses is of a particular value.
Claim 5
Dependent Claim
27 words
The apparatus of Claim 1, wherein said means for real-time collection of data is operable to latch information appearing on at least one of said memory buses.
Claim 6
Dependent Claim
27 words
The apparatus of Claim 1. wherein said means for real-time collection of data is operable to trace information appearing on at least one of said memory buses.
Claim 7
Dependent Claim
18 words
The apparatus of Claim 1. wherein said means for real-time correction of data comprises a logical interface unit.
Claim 8
Dependent Claim
48 words
7 The apparatus of Claim 6. wherein said logicai interface unit comprises a random access memory electrically communicating with said data processor interface buffer means, said random access memory operable to store information appearing on one of said memory buses wren said data processor executes a write commano.
Claim 9
Dependent Claim
36 words
The apparatus of Claim 7. wherein said logical interface unit further comprises a first FIFO memory, said first FIFO memory being selectively operable to continuously receive information appearing on at least one of said memory buses.
Claim 10
Dependent Claim
39 words
9 The aooaratus for Claim 8 wherein said first F!FO memory is further selectively operable to receive information appearing on one of said memory cuses when the information appearing on one of said buses is of a predetermined value.
Claim 11
Dependent Claim
36 words
The apparatus of Claim 9, wherein said logical interface unit further comprises a second FIFO memory, said second FIFO memory being selectively operable to continuously receive information appearing on at least one of said memory buses.
Claim 12
Dependent Claim
37 words
The apparatus of Claim 10. wherein said second FIFO memory is further selectively operable to receive Information appearing on one of said memory buses when the information appearing on one of said buses of a predetermined value
Claim 13
Dependent Claim
27 words
The apparatus of Claim 1. wherein said means for real-time collection of data comprises a XRAM in the electrical communication with said data processor interface buffer means.
Claim 14
Dependent Claim
33 words
13 The apparatus of Claim 12. wherein said means for real-time collection of data further comprises a data orocessor simulator. said data processor simulator operable to simulate the output of said data processor.
Claim 15
Dependent Claim
35 words
The apparatus of Claim 13. wherein said means for real-time collection of data further comprises a logical interface unit operable to permit selective collection of data from said data processor and said data processor simulator.
Claim 16
Dependent Claim
35 words
The apparatus of Claim 14. wherein said means for real-time collection of data further comprises a computer interface module operable to interface said logical interface unit and said external random access memory with said computer
Claim 17
Independent Claim
146 words
An apparatus for testing missile systems, said apparatus electrically communicating with the operand memory and the program memory of a missile data processor through a plurality of memory buses, said apparatus further electrically communicating with a computer, said apparatus comprising: a data processor interface buffer electrically communicating with said operand memory and said program memory: an external random access memory electrically communicating with said program memory; a logical interface unit for collecting data from said operand memory and said program memory in real-time. said logical interface unit electrically communicating with said data processor interface buffer; a data processor simulator operable to simulate the output of said data processor, said data processor simulator electrically communicating with said logical interface unit and said external random access memory: and a computer interface module operable to interface said logical interface unit and said external random access memory with said computer.
Claim 18
Independent Claim
146 words
An apparatus for testing missile systems, said apparatus electrically communicating with the operand memory and the program memory of a missile data processor through a plurality of memory buses, said apparatus further electrically communicating with a computer, said apparatus comprising: a data processor interface buffer electrically communicating with said operand memory and said program memory: an external random access memory electrically communicating with said program memory; a logical interface unit for collecting data from said operand memory and said program memory in real-time. said logical interface unit electrically communicating with said data processor interface buffer; a data processor simulator operable to simulate the output of said data processor, said data processor simulator electrically communicating with said logical interface unit and said external random access memory: and a computer interface module operable to interface said logical interface unit and said external random access memory with said computer.
Claim 19
Dependent Claim
43 words
The apparatus for Claim 16. wherein said data processor interface buffer comprises a plurality of translators operable to convert the logic levels associated with said data processor into the logic levels associated with said external random access memory and said logical interface unit.
Claim 20
Dependent Claim
39 words
The apparatus of Claim 17. further comprising a first multiplexer operable to multiplex information from said data processor and said data processor simulator. said first multiplexer electrically communicating with said logical interface unit and said external random access memory.
Claim 21
Dependent Claim
37 words
19 The apparatus of Claim 18. wherein said apparatus further comprises a second multiplexer operable to multiplex information from said data processor and said data processor simulator, said second multiplexer electrically communicating with said logical interface unit.
Claim 22
Dependent Claim
33 words
The apparatus in Claim 19. wnerein said logical interface unit is operable to cause said computer to pause when the information appearing on one of said memory buses is of a predetermined value.
Claim 23
Dependent Claim
32 words
The apparatus of Claim 20. wherein said logical interface unit is operable to count the number of occurrences that information appearing on one of said memory buses is of a predetermined value.
Claim 24
Dependent Claim
22 words
The apparatus of Claim 21. wherein said logical interface unit is operable to latch information appearing on one of said memory buses.
Claim 25
Dependent Claim
22 words
The apparatus of Claim 22. wherein said logical Interface unit is operable to trace information appearing on one of said memory buses.
Claim 26
Dependent Claim
46 words
The apparatus of Claim 23. wherein said logical interface unit comprises a random access memory electrically communicating with said data processor interface buffer. said random access memory operable to store information appearing on one of said memory buses when the data processor executes a write command.
Claim 27
Dependent Claim
34 words
The apparatus of Claim 24. wherein said logical interface unit further comprises a first FIFO memory, said first FIFO memory being selectively operable to continuously receive information appearing on one of said memory buses.
Claim 28
Dependent Claim
37 words
The apparatus for Claim 25, wherein said first FIFO memory is further selectively operable to receive information appearing on one of said memory buses when the Information appearing on one of said buses of a predetermined value
Claim 29
Dependent Claim
32 words
The apparatus of Claim 26. wherein said apparatus further comprises a second FIFO memory, said second FIFO memory being selectively operable to continuously receive information appearing on one of said memory buses.
Claim 30
Dependent Claim
39 words
The apparatus of Claim 27, wherein said second FIFO memory; s further operable to selectively receive information appearing on one of said memory buses wren the information appearing on one of said memory buses is of a predetermined value
Claim 31
Dependent Claim
14 words
The apparatus of Claim 28, wherein said external randcm access memory comprises a XRAM.
Claim 32
Dependent Claim
24 words
The apparatus of Claim 16. wherein said apparatus permits the contents of said program memory to be dumped onto said external random access memory.
Claim 33
Dependent Claim
32 words
The apparatus of Claim 16, wherein said logical interface ur: s further operable to deliver information to said data processor so that the hardware driven by said data processor may be tested.
Claim 34
Independent Claim
72 words
A method for testing missile systems, said missile having a data processor electrically communicating with a memory through a plurality of memory buses. said method comprising the steps of: receiving information appearing on one of said memory buses though a data processor interface buffer: collecting in real-time the information appearing on one of said memory buses through said data processor interface buffer: and delivering said information collected in real-time to a computer.
Claim 35
Independent Claim
72 words
A method for testing missile systems, said missile having a data processor electrically communicating with a memory through a plurality of memory buses. said method comprising the steps of: receiving information appearing on one of said memory buses though a data processor interface buffer: collecting in real-time the information appearing on one of said memory buses through said data processor interface buffer: and delivering said information collected in real-time to a computer.
Claim 36
Dependent Claim
44 words
The method of Claim 32. wherein said step of collecting in real-time the information appearing on one of said memory buses comprises the step of generating a pause signai when the information appearing on one of said memory buses is of a predetermined value.
Claim 37
Dependent Claim
44 words
The method of Claim 32. wherein said step of collecting in real-time the information appearing on one of said memory buses comprises the step of generating a signal wren the information appearing on one of said memory buses occurs a predetermined number of times.
Claim 38
Dependent Claim
48 words
The method of Claim 32, wherein said step of collecting in real-time information appearing on one of said memory buses comprises the step of latching information appearing on one of said memory buses when the information appearing on one of said memory buses is of a predetermined value.
Claim 39
Dependent Claim
33 words
The method of Claim 32, wherein said step of collecting in real-time information appearing on one of said memory buses comprises the step of tracing information appearing on one of said memory buses.
Claim 40
Dependent Claim
22 words
The method of Claim 32, comprising the additional step of dumping the contents of said memory onto an external random access memory.
Claim 41
Dependent Claim
35 words
The method of Claim 32. wherein said method comprises the additional step of delivering instructions from a computer to said data processor so that the hardware being driven by said data processor may be tested.
References Cited (Backward Citations)
No citation records indexed.
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