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EP0286857A2
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Image signal processor
Assignee: Sharp Corp
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Filing: 1988-03-16
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Granted: —
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Expires: 2008-03-16
Abstract
Abstract An image signal processor which comprises a memory device (9) for storing an image signal representative of a picture during one field period; an operating unit (18) for generating a READ-OUT command necessary to read out contents stored in the memory device from the memory device; a selector (SW 1) for selectively switching the memory device (9) between a WRITE-IN READY condition and a READ-OUT READY condition; and a switching control unit (5) for generating a control signal necessary to control the switching operation of the selector(SW 1). The switching control unit is adapted to receive the READ-OUT command and a vertical synchronizing signal included in a composite video signal. The selector performs the switching operation in synchronism with the initial vertical synchronizing signal applied immediately after the READ-OUT command has been inputted.
Inventors
- 👤 Takao Abumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 14:21
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/41; H04N21/414; H04N21/4143; H04N1/00; H04N1/46; H04N1/64; H04N1/646; H04N1/648; H04N5/00; H04N5/44; H04N5/4448
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
134 words
An image signal processor which comprises: a memory means (9) for storing an image signal representative of a picture during one field period; an operating means(18) for generating a READ-OUT command necessary to read out contents stored in the memory means from the memory means; a switching means (SW 1) for selectively switching the memory means between a WRITE-IN READY condition and a READ-OUT READY condition; and a switching control means (15) for generating a control signal necessary to control the switching operation of the switching means, said switching control means being adapted to receive the READ-OUT command and a vertical synchronizing signal included in a composite video signal, and said switching means performing the switching operation in synchronism with the initial vertical synchronizing signal applied immediately after the READ-OUT command has been inputted.
Claim 2
Dependent Claim
134 words
An image signal processor which comprises: a memory means (9) for storing an image signal representative of a picture during one field period; an operating means(18) for generating a READ-OUT command necessary to read out contents stored in the memory means from the memory means; a switching means (SW 1) for selectively switching the memory means between a WRITE-IN READY condition and a READ-OUT READY condition; and a switching control means (15) for generating a control signal necessary to control the switching operation of the switching means, said switching control means being adapted to receive the READ-OUT command and a vertical synchronizing signal included in a composite video signal, and said switching means performing the switching operation in synchronism with the initial vertical synchronizing signal applied immediately after the READ-OUT command has been inputted.
Claim 3
Dependent Claim
146 words
An image signal processor which comprises: a converting means for demodulating a composite color video signal into color difference signals and for matrixing the difference signals with the composite color video signal so as to cause the color difference signals to be converted into respective primary color signals having carrier color signal components superimposed thereon; a digitizing circuit for digitizing an output from the converting means at a predetermined threshold level; a clock pulse generating circuit for generating clock pulses synchronized with a color burst signal included in the composite color video signal and having a frequency n times the frequency of the color burst signal, wherein n represents a positive integer not smaller than 2; and a memory means for sampling and storing an output from the digitizing circuit when the clock pulses from the clock pulse generating circuit are applied as sampling clock pulses.
Claim 4
Dependent Claim
146 words
An image signal processor which comprises: a converting means for demodulating a composite color video signal into color difference signals and for matrixing the difference signals with the composite color video signal so as to cause the color difference signals to be converted into respective primary color signals having carrier color signal components superimposed thereon; a digitizing circuit for digitizing an output from the converting means at a predetermined threshold level; a clock pulse generating circuit for generating clock pulses synchronized with a color burst signal included in the composite color video signal and having a frequency n times the frequency of the color burst signal, wherein n represents a positive integer not smaller than 2; and a memory means for sampling and storing an output from the digitizing circuit when the clock pulses from the clock pulse generating circuit are applied as sampling clock pulses.
Claim 5
Dependent Claim
121 words
An image signal processor which comprises: a clock pulse generating means for generating first clock pulses and also for generating second clock pulses synchronized with the first clock pulses and having a frequency n times the frequency of the first clock pulses, wherein n represents a positive integer not smaller than 2; a quasi-intermediate color generating means for superimposing the first clock pulses on a given image signal to provide a superimposed image signal and also for digitizing the superimposed image signal to provide a digitized signal; and a memory means for sampling and storing the digitized signal from the quasi-intermediate color generating means when the second clock pulses from the clock pulse generating means are applied as sampling clock pulses.
Claim 6
Dependent Claim
121 words
An image signal processor which comprises: a clock pulse generating means for generating first clock pulses and also for generating second clock pulses synchronized with the first clock pulses and having a frequency n times the frequency of the first clock pulses, wherein n represents a positive integer not smaller than 2; a quasi-intermediate color generating means for superimposing the first clock pulses on a given image signal to provide a superimposed image signal and also for digitizing the superimposed image signal to provide a digitized signal; and a memory means for sampling and storing the digitized signal from the quasi-intermediate color generating means when the second clock pulses from the clock pulse generating means are applied as sampling clock pulses.
Claim 7
Dependent Claim
150 words
An image signal processor which comprises: a clock pulse generating means for generating clock pulses; and a quasi-intermediate color generating means responsive to the clock pulses from the clock pulse generating means, said quasi-intermediate color generating means comprising: a clock pulse superimposing means including a direct current inhibiting capacitor for cutting off a direct current component contained in the clock pulses supplied from the clock pulse generating means, and a transistor having a base to which a luminance signal is applied, and an emitter to which the clock pulses are applied through the direct current inhibiting capacitor, said transistor having a collector from which a superimposed luminance signal which corresponds to the luminance signal superimposed with the clock pulses is outputted; a matrix circuit for summing the superimposed luminance signal and color difference signals together to provide an added output; and an analog-to-digital converting circuit for digitizing the added output.
Claim 8
Dependent Claim
150 words
An image signal processor which comprises: a clock pulse generating means for generating clock pulses; and a quasi-intermediate color generating means responsive to the clock pulses from the clock pulse generating means, said quasi-intermediate color generating means comprising: a clock pulse superimposing means including a direct current inhibiting capacitor for cutting off a direct current component contained in the clock pulses supplied from the clock pulse generating means, and a transistor having a base to which a luminance signal is applied, and an emitter to which the clock pulses are applied through the direct current inhibiting capacitor, said transistor having a collector from which a superimposed luminance signal which corresponds to the luminance signal superimposed with the clock pulses is outputted; a matrix circuit for summing the superimposed luminance signal and color difference signals together to provide an added output; and an analog-to-digital converting circuit for digitizing the added output.
References Cited (Backward Citations)
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