Semiconductor integrated circuit having a data output buffer circuit

Claim 2

For a semiconductor circuit having a plurality of circuit com­ponents, the components coupled to a common power source along the same first and second current paths, an output buffer comprising: an output switching means for coupling the semicon­ductor circuit to an output terminal for supplying an output signal in response to a signal supplied by the semiconductor circuit, said out­put switching means including two output electrodes, the first elec­trode coupled to the common power source along a third circuit path and the second electrode coupled to the common power source along a fourth path, the first and second paths being independent of the third and fourth paths.

Claim 3

The output buffer according to claim 1 wherein said output switching means comprises a first and second transistor connected in series.

Claim 4

The output buffer according to claim 2 wherein the plurality of circuit components includes two gate circuits, each gate circuit associated with a respective one of said first and second series-con­nected transistors for generating a signal to control the switching of the corresponding transistor.

Claim 5

A semiconductor device including a semiconductor integrated circuit having a plurality of circuit components, said device comprising: first and second power source pads coupled to the high potential side of an external power source by means of respective wirings; first and second reference pads coupled to the refer­ence potential side of said external power source by means of respective wirings; and a data output buffer having a data output terminal for supplying an output signal in response to a signal supplied by the semiconductor integrated circuit, said data output buffer being cou­pled between the first power source pad and the first reference pad and said plurality of circuit components being coupled between the second power source pad and the second reference pad.

Claim 6

A semiconductor device including a semiconductor integrated circuit having a plurality of circuit components, said device comprising: first and second power source pads coupled to the high potential side of an external power source by means of respective wirings; first and second reference pads coupled to the refer­ence potential side of said external power source by means of respective wirings; and a data output buffer having a data output terminal for supplying an output signal in response to a signal supplied by the semiconductor integrated circuit, said data output buffer being cou­pled between the first power source pad and the first reference pad and said plurality of circuit components being coupled between the second power source pad and the second reference pad.

Claim 7

The semiconductor device according to claim 4 wherein the data output buffer circuit comprises first and second transistors connected in series.

Claim 8

The semiconductor device according to claim 5 wherein said first series-connected transistor is coupled between the first power source pad and the data output terminal and said second series-con­nected transistor is coupled between the first reference pad and the data output terminal.

Claim 9

The semiconductor device according to claim 5 wherein said plurality of circuit components includes two gate circuits, each gate circuit associated with a respective one of said first and second series-connected transistors for generating a signal to control the switching of the corresponding transistor.

Claim 10

The semiconductor device according to claim 4 wherein the reference potential is ground potential.

Claim 11

The semiconductor device according to claim 4 wherein the semiconductor integrated circuit is a memory having a multi-bit data output system.

Claim 12

The semiconductor device according to claim 4 wherein the first and second power source pads are connected to a first lead of high potential using first and second bonding wires respectively, and the first and second reference pads are connected to a second lead of reference potential using third and fourth bonding wires respectively.

Claim 13

A semiconductor device including a semiconductor integrated circuit having a plurality of circuit components, said device comprising: first and second power source pads coupled to the high potential side of an external power source by means of respective wirings; first and second reference pads coupled to the refer­ence potential side of said external power source by means of respective wirings; a data output buffer having a data output terminal comprising first and second transistors coupled in series between the first power source pad and the first reference pad for supplying an output signal in response to a signal supplied by the semiconductor integrated circuit; and first and second gate circuits, each gate circuit associ­ated with a respective one of said first and second series connected transistors for generating a signal to control the switching of the corresponding transistor, said gate circuits being circuit components of said semiconductor integrated circuit, said first gate circuit cou­pled between said second power source pad and said first reference pad, said second gate circuit and remaining circuit components cou­pled between said second power source pad and said second refer­ence pad.

Claim 14

A semiconductor device including a semiconductor integrated circuit having a plurality of circuit components, said device comprising: first and second power source pads coupled to the high potential side of an external power source by means of respective wirings; first and second reference pads coupled to the refer­ence potential side of said external power source by means of respective wirings; a data output buffer having a data output terminal comprising first and second transistors coupled in series between the first power source pad and the first reference pad for supplying an output signal in response to a signal supplied by the semiconductor integrated circuit; and first and second gate circuits, each gate circuit associ­ated with a respective one of said first and second series connected transistors for generating a signal to control the switching of the corresponding transistor, said gate circuits being circuit components of said semiconductor integrated circuit, said first gate circuit cou­pled between said second power source pad and said first reference pad, said second gate circuit and remaining circuit components cou­pled between said second power source pad and said second refer­ence pad.

Claim 15

The semiconductor device according to claim 11 wherein said first series-connected transistor is coupled between the first power source pad and the data output terminal and said second series-con­nected transistor is coupled between the first reference pad and the data output terminal.