Dynamic random access memory device having a plurality of improved one-transistor type memory cells

Claim 2

A dynamic random access memory device comprising a semiconductor substrate of one conductivity type and having front and back major surfaces, an impurity region of a conductivity type opposite to said substrate formed in an inner portion of said substrate and having a net-­like plane shape, means for leading out a part of said impurity region to a portion of said front major surface of said substrate, and a plurality of memory cells each having a transfer gate transistor and a trench capacitor, said transfer gate transistor including a pair of source and drain regions of a conductivity type opposite to said substrate and formed on said front major surface of said substrate, said trench capacitor including a trench formed in said substrate from said front major surface into said impurity region such that a section of the wall of said trench is constituted by said impurity region, a dielectric film formed on said section of said wall of said trench and a capacitor electrode formed on said dielectric film within said trench and electrically connected to one of said source and drain regions of said transfer gate transistor.

Claim 3

A device of Claim 1, in which each of said trench includes a lower portion having the bottom of said trench and surrounded by a lower side wall, and an upper portion positioned between said front major surface of said substrate and said lower portion and surrounded by an upper side wall, and further comprising an insulating layer having a thickness thicker than the thickness of said dielectric film and formed on said upper side wall of said trench.

Claim 4

A device of Claim 1, in which the bottom wall of said trench and a lower side wall adjacent to said bottom wall of said trench are constituted by said impurity region.

Claim 5

A device of Claim 3, in which an upper side wall of said trench between said front major surface and said lower side wall is constituted by a highly doped impurity region of said one conductivity type and having a higher impurity concentration than the impurity concentration of said substrate.

Claim 6

A device of Claim 4 further comprising an insulating layer provided on said highly doped impurity region within said trench and having a thickness thicker than the thickness of said dielectric film.

Claim 7

A device of Claim 1 further comprising a back electrode formed on said back major surface of said substrate for applying a back-gate-bias voltage to said back electrode.

Claim 8

A device of Claim 1 further comprising a means for supplying a fixed potential to said impurity region through said leading out means.

Claim 9

A device of Claim 1, in which said means includes a conductive material connecting said part of said impurity region and an electrode on said front major surface of said substrate.

Claim 10

A device of Claim 8, in which said conductive material is made of polycrystalline silicon doped with an impurity.

Claim 11

A device of Claim 1, in which said means includes a groove provided from said front major surface of said substrate to said impurity region adjacent to said part of said impurity region, an insulating film covering an entire wall of said groove, a conductor material formed on said insulating film within said groove, a semiconductor region having a conductivity type opposite to said substrate and formed on said front major surface of said substrate and adjacent to said groove, means for applying a voltage to said conductor material to form an inversion layer of a conductivity type opposite to said substrate along said groove between said semiconductor region on said front major surface of said substrate and said part of said impurity region inner said substrate, and means for applying a fixed potential to said semiconductor region.

Claim 12

A dynamic random access memory device comprising a semiconductor substrate of one conductivity type having a front major surface of said one conductivity type and a back major surface of said one conductivity type, a plurality of transfer gate transistors formed on said front major surface, each of said transistors including a pair of source and drains regions of a conductivity type opposite to said one conductivity type, a channel region positioned between said source and drain regions, a gate insulating film formed on said channel region and a gate electrode formed on said gate insulating film and coupled to a word line, a plurality of trenches formed in said substrate from said front major surface inwardly, each of said trenches having an upper side wall surrounding an upper portion of said trench and extending from said front major surface of said substrate, a bottom wall and a lower side wall surrounding a lower portion of said trench and positioned between said upper side wall and said bottom wall, a plurality of thick insulating layers formed on said upper side walls of respective said trenches, a plurality of capacitors, each of said capacitor including a dielectric film having a thickness thinner than that of said thick insulating layer and formed on said lower side wall and on said bottom wall of said trench, a conductive material formed on said dielectric film within said trench and an impurity region having a conductivity type opposite to said one conductivity type and formed at said lower side wall and at said bottom wall of said trench such that said lower side wall and said bottom wall of said trench are constituted by said impurity region, each of said impurity regions being extended from said lower side wall of said trench into said substrate and forming a ring-plan shape, and respective said impurity regions and adjacent said impurity regions being connected each other at their outer parts so that a chain-like plane construction is constituted by said impurity regions and that a plurality of substrate sections of said one conductivity type remain between said impurity regions, means for leading out said chain-like plane construction by said impurity regions at a led-out section thereof to said front major surface of said substrate, and means for connecting said conductive materials of said respective capacitors to said source or drain regions of corresponding said transistors.

Claim 13

A dynamic random access memory device comprising a semiconductor substrate of one conductivity type having a front major surface of said one conductivity type and a back major surface of said one conductivity type, a plurality of transfer gate transistors formed on said front major surface, each of said transistors including a pair of source and drains regions of a conductivity type opposite to said one conductivity type, a channel region positioned between said source and drain regions, a gate insulating film formed on said channel region and a gate electrode formed on said gate insulating film and coupled to a word line, a plurality of trenches formed in said substrate from said front major surface inwardly, each of said trenches having an upper side wall surrounding an upper portion of said trench and extending from said front major surface of said substrate, a bottom wall and a lower side wall surrounding a lower portion of said trench and positioned between said upper side wall and said bottom wall, a plurality of thick insulating layers formed on said upper side walls of respective said trenches, a plurality of capacitors, each of said capacitor including a dielectric film having a thickness thinner than that of said thick insulating layer and formed on said lower side wall and on said bottom wall of said trench, a conductive material formed on said dielectric film within said trench and an impurity region having a conductivity type opposite to said one conductivity type and formed at said lower side wall and at said bottom wall of said trench such that said lower side wall and said bottom wall of said trench are constituted by said impurity region, each of said impurity regions being extended from said lower side wall of said trench into said substrate and forming a ring-plan shape, and respective said impurity regions and adjacent said impurity regions being connected each other at their outer parts so that a chain-like plane construction is constituted by said impurity regions and that a plurality of substrate sections of said one conductivity type remain between said impurity regions, means for leading out said chain-like plane construction by said impurity regions at a led-out section thereof to said front major surface of said substrate, and means for connecting said conductive materials of said respective capacitors to said source or drain regions of corresponding said transistors.