Patent EP0283228A2 successfully refreshed from Google Patents.
EP0283228A2
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EP
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Dynamic type decoder circuit
Assignee: Fujitsu Ltd
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Filing: 1988-03-14
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Granted: —
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Expires: 2008-03-14
Abstract
Abstract A dynamic type decoder circuit including a first power source line (Vcc); a second power source line; an output node (OUT); a first transistor (Q₆) connected between the first power source line and the output node, the first transistor being turned on during a reset period to reset the output potential of the output node (OUT) to a predetermined potential level; a second transistor (Q₅) connected to a second power source line, the second transistor being turned on during a decoding period; a plurality of decoding transistors (Q₁....Q₄) connected in series between the output node (OUT) and the second transistor (Q₅), the decoding transistors being controlled in accordance with address signals (A,B,C,D); and means (I₁...I₄, G₁...G₄) for forcibly turning on one or more of said decoding transistors (Q₁...Q₃) connected between the output node and that one of the decoding transistors (Q₄) directly connected to the second transistor, during the reset period, regardless of the potential levels of the address signals (A,B,C,D).
Inventors
- 👤 Yoshiaki Okano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 20:10
CPC Classifications
G; G11; G11C; G11C7/00; G11C8/00; G11C8/10; G11C8/06
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
147 words
A dynamic type decoder circuit comprising: a first power source line; a second power source line; an output node; a first transistor connected between said first power source line and said output node, said first transistor being turned on during a reset period to reset the output potential of said output node to a predetermined potential level; a second transistor connected to said second power source line, said second transistor being turned on during a decoding period; a plurality of decoding transistors connected in series between said output node and said second transistor, said decoding transistors being controlled in accordance with address signals; and means for forcibly turning on at least one of said decoding transistors, connected between said output node and that one of said decoding transistors directly connected to said second transistor, during said reset period regardless of the potential levels of said address signals.
Claim 2
Dependent Claim
147 words
A dynamic type decoder circuit comprising: a first power source line; a second power source line; an output node; a first transistor connected between said first power source line and said output node, said first transistor being turned on during a reset period to reset the output potential of said output node to a predetermined potential level; a second transistor connected to said second power source line, said second transistor being turned on during a decoding period; a plurality of decoding transistors connected in series between said output node and said second transistor, said decoding transistors being controlled in accordance with address signals; and means for forcibly turning on at least one of said decoding transistors, connected between said output node and that one of said decoding transistors directly connected to said second transistor, during said reset period regardless of the potential levels of said address signals.
Claim 3
Dependent Claim
38 words
A dynamic type decoder circuit according to claim 1, further comprising means for forcibly turning on said decoding transistor directly connected to said second transistor during said reset period regardless of the potential levels of said address signals.
Claim 4
Dependent Claim
94 words
A dynamic type decoder circuit according to claim 1, further comprising a plurality of other decoding transistors connected in series between said output node and said second transistor and connected in parallel with said plurality of decoding transistors, said other decoding transistors being controlled in accordance with address signals; and means for forcibly turning on at least one of said other decoding transistors, connected between said output node and that one of said other decoding transistors directly connected to said second transistor,during said reset period regardless of the potential levels of said address signals.
Claim 5
Dependent Claim
45 words
A dynamic type decoder circuit according to claim 3, further comprising means for forcibly turning on said decoding transistor and said other decoding transistor which are directly connected to said second transistor during said reset period, regardless of the potential levels of said address signals.
Claim 6
Dependent Claim
111 words
A dynamic type decoder circuit according to claim 1, wherein said first transistor and said second transistor are a P-channel type transistor and an N-channel type transistor, respectively, and said means for forcibly turning transistors on comprises one or more inverters each arranged to receive one of the address signals and one or more NAND gates each arranged to receive a clock signal supplied to said first transistor and the output signal from a corresponding one of said inverters, each output signal of said NAND gates being supplied to a corresponding one of said decoding transistors connected between said output node and said decoding transistor directly connected to said second transistor.
Claim 7
Dependent Claim
111 words
A dynamic type decoder circuit according to claim 1, wherein said first transistor and said second transistor are an N-channel type transistor and a P-channel type transistor, respectively, and said means for forcibly turning transistors on comprises one or more inverters each arranged to receive one of the address signals and one or more NOR gates each arranged to receive a clock signal supplied to said first transistor and the output signal from a corresponding one of said inverters, each output signal of said NOR gates being supplied to a corresponding one of said decoding transistors connected between said output node and said decoding transistor directly connected to said second transistor.
Claim 8
Dependent Claim
105 words
A dynamic type decoder circuit according to claim 2, wherein said first transistor and said second transistor are a P-channel type transistor and an N-channel type transistor, respectively, and said means for forcibly turning transistors on comprises a plurality of inverters each arranged to receive one of the address signals and a plurality of NAND gates each arranged to receive a clock signal supplied to said first transistor and the output signal from a corresponding one of said inverters, each output signal of said NAND gates being supplied to one a corresponding of said decoding transistors connected between said output node and said second transistor.
Claim 9
Dependent Claim
101 words
A dynamic type decoder circuit according to claim 2, wherein said first transistor and said second transistor are an N-channel type transistor and a P-channel type transistor, respectively, and said means for forcibly turning transistors on comprises a plurality of inverters each arranged to receive one of the address signals and a plurality of NOR gates each arranged to receive a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NOR gates being supplied to one of said decoding transistors connected between said output node and said second transistor.
Claim 10
Dependent Claim
120 words
A dynamic type decoder circuit according to claim 3, wherein said first transistor and said second transistor are a P-channel type transistor and an N-channel type transistor, respectively, and said means for forcibly turning transistors on comprises one or more inverters each arranged to receive one of the address signals and one or more NAND gates each arranged to receive a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NAND gates being supplied to one of said decoding transistors and said other decoding transistors each connected between said output node and one of said decoding transistor and said other decoding transistor directly connected to said second transistor.
Claim 11
Dependent Claim
120 words
A dynamic type decoder circuit according to claim 3, wherein said first transistor and said second transistor are an N-channel type transistor and a P-channel type transistor, respectively, and said means for forcibly turning transistors on comprises one or more inverters each arranged to receive one of the address signals and one or more NOR gates each arranged to receive a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NOR gates being supplied to one of said decoding transistors and said other decoding transistors each connected between said output node and one of said decoding transistor and said other decoding transistor directly connected to said second transistor.
Claim 12
Dependent Claim
107 words
A dynamic type decoder circuit according to claim 4, wherein said first transistor and said second transistor are a P-channel type transistor and an N-channel type transistor, respectively, and said means for forcibly turning transistors on comprises a plurality of inverters each arranged to receive one of the address signals and a plurality of NAND gates each arranged to receive a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NAND gates being supplied to one of said decoding transistors and said other decoding transistors each connected between said output node and said second transistor.
Claim 13
Dependent Claim
107 words
A dynamic type decoder circuit according to claim 4, wherein said first transistor and said second transistor are an N-channel type transistor and a P-channel type transistor, respectively, and said means for forcibly turning transistors on comprises a plurality of inverters each arranged to receive one of the address signals and a plurality of NOR gates each arranged to receive a clock signal supplied to said first transistor and the output signal from one of said inverters, each output signal of said NOR gates being supplied to one of said decoding transistors and said other decoding transistors each connected between said output node and said second transistor.
References Cited (Backward Citations)
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