Semiconductor integrated circuit with a plurality of circuit blocks having equivalent functions

Claim 2

A semiconductor integrated circuit having power lines, the circuit comprising: a plurality of circuit blocks each having equivalent functions; first switch means corresponding to each circuit block for coupling power from said power lines to the corresponding circuit block; and switch control means corresponding to each first switch means for selectively controlling the activation of the corresponding first switch means.

Claim 3

A semiconductor integrated circuit having power lines, the circuit comprising: a plurality of circuit blocks each having equivalent functions; first switch means corresponding to each circuit block for coupling power from said power lines to the corresponding circuit block; switch control means corresponding to each first switch means for selectively controlling the activation of the corresponding first switch means; and a block addressing means coupled to each of said plurality of circuit blocks to selectively address at least one of said circuit blocks.

Claim 4

A semiconductor integrated circuit having power lines, the circuit comprising: a plurality of circuit blocks each having equivalent functions; first switch means corresponding to each circuit block for coupling power from said power lines to the corresponding circuit block; switch control means corresponding to each first switch means for selectively controlling the activation of the corresponding first switch means; and a block addressing means coupled to each of said plurality of circuit blocks to selectively address at least one of said circuit blocks.

Claim 5

The semiconductor integrated circuit according to claim 1 or 2 further comprising: means for maintaining a circuit block at a fixed potential when the corresponding first switch means is not activated.

Claim 6

The semiconductor integrated circuit according to claim 3 wherein said fixed potential is the ground potential.

Claim 7

The semiconductor integrated circuit according to claim 1 or 2 further comprising: second switch means coupled to the circuit block for impeding the flow of an output signal from the circuit block when the correponding first switch means is not activated.

Claim 8

The semiconductor integrated circuit according to claim 5 wherein said second switch means is a CMOS switch comprising a P-type transistor and an N-type transistor connected in parallel.

Claim 9

The semiconductor integrated circuit according to claim 1 or 2 further comprising: at least one output transistor coupled to the circuit block; and means for selectively controlling the gate potentials of said at least one output transistor so as to control the activation of said output transistor.

Claim 10

The semiconductor integrated circuit according to claim 1 or 2 wherein the plurality of circuit blocks are memory blocks formed on a semiconductor wafer, the integrated circuit being a full wafer memory.

Claim 11

The semiconductor integrated circuit according to claim 1 or 2 wherein said first switch means comprises a transistor.

Claim 12

The semiconductor integrated circuit according to claim 1 or 2 wherein said switch control means comprises a programmable element.

Claim 13

The semiconductor integrated circuit according to claim 10 wherein said programmable element is a fuse.

Claim 14

The semiconductor integrated circuit according to claim 11 wherein said fuse may be blown by irradiation.

Claim 15

The semiconductor integrated circuit according to claim 3 wherein said means for maintaining a circuit block at fixed poten­tial comprises a transistor whose control gate is coupled to the corre­sponding switch control means and whose electrodes are coupled between the circuit block and a ground.

Claim 16

The semiconductor integrated circuit according to claim 1 or 2 wherein each of said circuit blocks comprises a memory cell array.

Claim 17

The semiconductor integrated circuit according to claim 1 or 2 wherein each of said circuit blocks comprises shift registers.

Claim 18

The semiconductor integrated circuit according to claim 1 or 2 wherein each of said circuit blocks comprises a gate array.

Claim 19

The semiconductor integrated circuit according to claim 1 wherein said switch control means includes a programmable ele­ment for selectively controlling the activation of the corresponding first switch means according to the logic level of a test control signal applied to said switch control means when said programmable element is in an unprogrammed state.

Claim 20

The semiconductor integrated circuit according to claim 17 wherein said switch control means further generates an output which deactivates the corresponding first switch means when the pro­grammable element is in a programmed state.

Claim 21

The semiconductor integrated circuit according to claim 2 wherein said switch control means includes a programmable ele­ment for selectively controlling the activation of the corresponding first switch means according to the logic level of a test control signal common to each switch control means and an address signal from said block addressing means which selectively addresses at least one of said circuit blocks when said programmable element is in an unprogrammed state.

Claim 22

The semiconductor integrated circuit according to claim 19 wherein said switch control means further generates an output which deactivates the corresponding first switch means when the pro­grammable element is in a programmed state.

Claim 23

The semiconductor integrated circuit according to claim 1 wherein said switch control means comprises: a resistive element, a programmable element, and a tran­sistor respectively coupled in series between said power lines, an inverted test signal being applied to the gate of said series-coupled transistor.

Claim 24

The semiconductor integrated circuit according to claim 21 wherein said first switch means is coupled to a point between said series-coupled resistive element and programmable element.

Claim 25

The semiconductor integrated circuit according to claim 2 wherein said switch control means comprises: a resistive element, a programmable element, and an N-type and P-type transistor coupled in parallel, said resistive element, programmable element, and parallel transistor combination being respectively coupled in series between said power lines, an inverted test signal common to each of said switch control means being applied to the gate of said N-type transistor coupled in parallel and a selection signal corresponding to an addressed circuit block being applied to said P-type transistor coupled in parallel.

Claim 26

The semiconductor integrated circuit according to claim 23 wherein said first switch means is coupled to a point between said series-coupled resistive element and programmable element.

Claim 27

The semiconductor integrated circuit according to claim 2 wherein said switch control means comprises: a programmable element and a resistive element respec­tively coupled in series between said power lines; a first and second P-type transistor and a first and second N-type transistor respectively coupled in series between said power lines; a third P-type transistor coupled in parallel with said first and second P-type transistor; a third N-type transistor coupled in parallel with said second N-type transistor; a latch circuit for latching a selection signal correspond­ing to an addressed circuit block, the output of said latch circuit being coupled to the gates of the second P-type transistor and the third N-type transistor, the selection signal being latched in response to a test signal common to each of said switch control means, the inverted test signal being applied to the gates of the first P-type transistor and the second N-type transistor, the control gates of said third P-type transistor and said first N-type transistor being coupled to a point between said series-coupled programmable element and resistive element.

Claim 28

The semiconductor integrated circuit according to claim 25 wherein said first switch means is coupled to a point between said series coupled second P-type transistor and first N-type transistor.

Claim 29

In a semiconductor integrated circuit having power lines, a plurality of circuit blocks each having equivalent functions, and a plurality of switch means, each switch means corresponding to a respective circuit block for coupling power from said power lines to the respective circuit block, a method of testing each respective cir­cuit block comprising the steps of: activating one of said switch means for coupling power to the corresponding circuit block to permit its operation; deactivating at least another of said switch means corre­sponding to a different circuit block; and testing the activated circuit block to determine if any malfunction exists in its operation.

Claim 30

In a semiconductor integrated circuit having power lines, a plurality of circuit blocks each having equivalent functions, and a plurality of switch means, each switch means corresponding to a respective circuit block for coupling power from said power lines to the respective circuit block, a method of testing each respective cir­cuit block comprising the steps of: activating one of said switch means for coupling power to the corresponding circuit block to permit its operation; deactivating at least another of said switch means corre­sponding to a different circuit block; and testing the activated circuit block to determine if any malfunction exists in its operation.

Claim 31

In a semiconductor integrated circuit having power lines, a plurality of circuit blocks each having equivalent functions and an addressing means for addressing said block, a switch means correspond­ing to each of said plurality of circuit blocks for coupling power from said power lines to each respective circuit block, a method of testing each respective circuit block comprising the steps of: addressing at least one of said circuit blocks to activate the corresponding switch means to couple power to said addressed cir­cuit block; and testing the addressed circuit block to determine if any malfunctions exist in its operation.

Claim 32

In a semiconductor integrated circuit having power lines, a plurality of circuit blocks each having equivalent functions and an addressing means for addressing said block, a switch means correspond­ing to each of said plurality of circuit blocks for coupling power from said power lines to each respective circuit block, a method of testing each respective circuit block comprising the steps of: addressing at least one of said circuit blocks to activate the corresponding switch means to couple power to said addressed cir­cuit block; and testing the addressed circuit block to determine if any malfunctions exist in its operation.

Claim 33

The method according to claim 27 further comprising the step of: repeating each of the prior steps until each of said plural­ity of circuit blocks has been tested.

Claim 34

The method according to claim 28 further comprising the step of: repeating each of the prior steps until each of said plural­ity of circuit blocks has been tested.