Optical switching system

Claim 1

An optical switching method in a telecommunication exchange, wherein input channels carrying packetized data are switched one by one to output channels, characterized in that the packets of a generic input channel (Ip) are compressed by time compressors (TC1, ..., TCn), are converted into optical signals (by EOp) and, at suitable instants, are sent to an optical switching network (RC) to be switched to a desired output channel, they are then reconverted into electrical signals and expanded by time expanders (TE1, ..., TEn) to their original duration, so as to form the output channel (on Oʹq), the switching of the input channels to the output channels being controlled by a centralized processor (EL) which controls the switching network through a driving circuit (LC).

Claim 6

The system as in any of claims 2 to 4, characterized in that said driving circuit (LC) comprises a decoder (DE) for decoding packet destination addresses and comprises for each input channel (I1, ..., In): - a SET-RESET flip-flop (SRp), whose reset input is enabled by octet absence in said FIFO memory (MEp), through a presence bit (on BPp), and by a signal (on BU) with the meaning of busy switching network, while the set input is enabled by octet presence in the memory, by a signal (on PR) of packet writing end in the memory, supplied by said centralized processor (EL), by a scanning periodic signal (on SC) with a period dependent on the desired transfer speed, and by the absence of the signal (on BU) with meaning of busy switching network, the signal at the output of this flip-flop being used to enable blocks (MEp, PSp, EOp) forming the associated time compressor (TC1, ..., TCn) and time expander (TE1, ..., TEn); - a gate (Pp), whose input is connected to the flip-flop output and whose output drives the line (BU) on which the signal relevant to switching network availability is present; - a register (RIp), which stores the destination addresses of the packets forming the input channel and two bits (on 3p, 4p) with the meaning of order number of the input channel greater than that of the output one and vice versa under the control of said centralized processor (EL), the transfer to the output of said data being enabled by the signal at the output of the flip-flop (SRp); - a combinational circuit (ACp, ADp, ORp), whose two outputs (X1p, X2p) are alternatively active in function of the two bits (on 3p, 4p) with the meaning of order number of the input channel greater or smaller than that of the output one, when enabled by the signal at the output of the flip-flop (SRp) or when enabled by the signal supplied by said decoder (DE), one of the two outputs being used to drive an electrode pair of said switching network.

Claim 7

The system as in any of claims 2 to 5, characterized in that said time expanders (TE1, ..., TEn) comprise an optical fibre connected to the switching network (RC), wherefrom high bit-rate packets are extracted for the opto-­electrical transducer, which sends them to a serial-to-­parallel converter apt to drive a FIFO memory, wherefrom the original packetized signal is extracted, the opto-­electrical transducer, the serial-to-parallel converter and the FIFO memory being enabled by the signal (on ABp) supplied by said flip-flop (SRp).