Semiconductor memory device with address generator

Claim 2

A semiconductor memory device comprising a) a memory cell array having a plurality of memory cells arranged in rows and columns, each of said memory cells storing a data bit, b) an addressing circuit operative to cause a plurality of data bits to be read out from said memory cell array, c) a plurality of selector modules coupled in series and having a first stage of selector module and a final stage of selector module, each of said selector modules being operative to decrease in number said data bits passing therethrough, said first stage of selector module coupled to said memory cell array, d) a plurality of decoder circuits each operative to produce an activation signal fed to each of said selector modules for specifying said data bits passing therethrough, e) a temporary data storage module coupled to said final stage of selector module and operative to latch said data bits supplied from said final stage of selector module, said data bits latched by the temporary data storage module being supplied to a destination, f) and a control circuit operative to produce an internal address signal on the basis of said data bits latched by said temporary data storage module as a result of a predetermined operation, characterized in that said addressing circuit and said selector modules except for at least said final stage of selector module are driven by said internal address signal and that said final stage of selector module is driven by a part of said data bits latched by said temporary data storage module.

Claim 3

A semiconductor memory device as set forth in claim 1, in which each of said memory cells is formed by a read only memory cell.

Claim 4

A semiconductor memory device as set forth in claim 2, in which said read only memory cell has a metal-insulator-­semiconductor structure, said insulator being formed to be thin or thick depending upon a logic level of said data bit preserved therein.

Claim 5

A semiconductor memory device as set forth in claim 1, in which said addressing circuit specifys a plurality of memory cells for reading out said data bits, each memory cell being selected from each of said rows.

Claim 6

A semiconductor memory device as set forth in claim 4, in which said rows are grouped by a predetermined number to form a plurality of memory cell groups and in which said first stage of selector module is operative to pass every single data bit from each of said memory cell groups.

Claim 7

A semiconductor memory device as set forth in claim 5, in which each of said selector modules comprising a plurality of gate transistors arranged in parallel.

Claim 8

A semiconductor memory device as set forth in claim 6, in which said first stage of selector module further comprises buffer circuits each coupled in series to each of said gate transistors.

Claim 9

A semiconductor memory device as set forth in claim 7, in which each of said buffer circuits is of the inverting type.

Claim 10

A semiconductor memory device as set forth in claim 8, in which said semiconductor memory device further comprises a plurality of inverting buffer circuits coupled in parallel between said final stage of selector module and said temporary data storage module.

Claim 11

A semiconductor memory device as set forth in claim 1, in which said temporary data storage module comprises a plurality of clocked flip-flop circuits coupled in parallel between said final stage of selector module and said destination.

Claim 12

A semiconductor memory device as set forth in claim 1, in which said semiconductor memory device serves as a microprogram control unit.

Claim 13

A semiconductor memory device as set forth in claim 11, in which said control circuit serves as a microprogram sequencer.

Claim 14

A semiconductor memory device comprising a) a memory cell array having a plurality of memory cells arranged in rows and columns, each of said memory cells storing a data bit, b) an addressing circuit operative to cause a plurality of data bits to be read out from said memory cell array, c) a plurality of selector modules coupled in series and having a first stage of selector module and a final stage of selector module, each of said selector modules being operative to decrease in number said data bits passing therethrough, said first stage of selector module coupled to said memory cell array, d) a plurality of decoder circuits each operative to produce an activation signal fed to each of said selector modules for specifying said data bits passing therethrough, e) a temporary data storage module coupled to said final stage of selector module and operative to latch said data bits supplied from said final stage of selector module, said data bits latched by the temporary data storage module being supplied to a destination, f) and a control circuit operative to produce internal address signals in succession on the basis of said data bits latched by said temporary data storage module as a result of a predetermined operation, characterized in that said addressing circuit and said selector modules except for at least said final stage of selector module are driven by said internal address signal and that said final stage of selector module is driven by said internal address signal lastly produced by said control circuit.

Claim 15

A semiconductor memory device comprising a) a memory cell array having a plurality of memory cells arranged in rows and columns, each of said memory cells storing a data bit, b) an addressing circuit operative to cause a plurality of data bits to be read out from said memory cell array, c) a plurality of selector modules coupled in series and having a first stage of selector module and a final stage of selector module, each of said selector modules being operative to decrease in number said data bits passing therethrough, said first stage of selector module coupled to said memory cell array, d) a plurality of decoder circuits each operative to produce an activation signal fed to each of said selector modules for specifying said data bits passing therethrough, e) a temporary data storage module coupled to said final stage of selector module and operative to latch said data bits supplied from said final stage of selector module, said data bits latched by the temporary data storage module being supplied to a destination, f) and a control circuit operative to produce internal address signals in succession on the basis of said data bits latched by said temporary data storage module as a result of a predetermined operation, characterized in that said addressing circuit and said selector modules except for at least said final stage of selector module are driven by said internal address signal and that said final stage of selector module is driven by said internal address signal lastly produced by said control circuit.

Claim 16

A semiconductor memory device comprising a) a memory cell array having a plurality of memory cells arranged in rows and columns, each of said memory cells storing a data bit, b) a plurality of bit lines each coupled to all of said memory cells in each row, c) a plurality of word lines each activating all of said memory cells in each column, d) a first decoder circuit responsive to a first internal address signal and operative to cause one of said word lines to activate said memory cells for reading out a plurality of data bits from said memory cell array, each of said data bits read out from said memory cell array appearing on each of said bit lines, and e) a plurality of decoder/selector modules coupled in series and having a first stage of decoder/selector module supplied with said data bits from said memory cell array and a final stage of decoder/selector module, each of said selector modules being responsive to each of second to final internal address signal and operative to decrease in number said data bits passing therethrough, characterized by an internal address generating module operative to produce said first to final internal address signals on the basis of said data bits passing through said final stage of decoder/selector module, wherein said final internal address signal is produced at the latest of all.

Claim 17

A semiconductor memory device comprising a) a memory cell array having a plurality of memory cells arranged in rows and columns, each of said memory cells storing a data bit, b) a plurality of bit lines each coupled to all of said memory cells in each row, c) a plurality of word lines each activating all of said memory cells in each column, d) a first decoder circuit responsive to a first internal address signal and operative to cause one of said word lines to activate said memory cells for reading out a plurality of data bits from said memory cell array, each of said data bits read out from said memory cell array appearing on each of said bit lines, and e) a plurality of decoder/selector modules coupled in series and having a first stage of decoder/selector module supplied with said data bits from said memory cell array and a final stage of decoder/selector module, each of said selector modules being responsive to each of second to final internal address signal and operative to decrease in number said data bits passing therethrough, characterized by an internal address generating module operative to produce said first to final internal address signals on the basis of said data bits passing through said final stage of decoder/selector module, wherein said final internal address signal is produced at the latest of all.