Four-transistor (4T) static ram cells

Claim 2

A structure for a four-transistor static random access memory cell formed on a semiconductor substrate, characterised by a layout in which two of said trans­istors employ one gate layer and another two of said transistors employ another independent gate layer.

Claim 3

The structure of claim 1 wherein said memory cell comprises two pass-gate transistors and a flip-­flop with two pull-down transistors, with the gates of said pass-gate transistors formed from one of said gate layers and with the gates of said pull-down transistors formed from the other of said gate layers.

Claim 4

The structure of claim 2 wherein said pass-gate transistors each have a gate overlying a gate oxide of a first thickness and said pull-down transistors each have a gate overlying a gate oxide of a second, independent thickness, and where said gates of said pull-down transistors are formed of a layer which is distinct from the layer of said gates of said pass-gate transistors.

Claim 5

The structure of claim 2 further characterised by placement of a first pass-gate transistor adjacent and in series with a first pull-down transistor, with said first pass-gate transistor and said first pull-down transistor sharing a first common node, and by placement of a second pass-gate transistor adjacent and in series with a second pull-down transistor, with said second pass-gate transistor and said second pull-down transistor sharing a second common node, with one pass-gate/pull-down transistor pair rotated 180° and placed adjacent the other pass-gate/pull-down transistor pair.

Claim 6

The structure of Claim 4 further characterized by said gate of said first pull-down transistor being an integral part of a larger first pull-down gate segment, and by said gate of said second pull-down transistor being an integral part of a larger second pull-down gate seg­ment, with said first pull-down gate segment routed to and positioned over said second common node, and with said second pull-down gate segment routed to and positioned over said first common node, with both of said gates of said pass-gate transistors connected together by a con­necting segment comprising the same material used to form said gates of said pass-gate transistors, thereby forming a continuous strip which serves as a wordline and wherein said wordline crosses over said first and second pull-down gate segments.

Claim 7

The structure of Claim 5 further characterized by two butting contacts, one providing an electrical con­nection between said first common node, said second pull-­down gate segment and a first resistive load, and another providing an electrical connection between said second common node, said first pull-down gate segment and a second resistive load.

Claim 8

A structure of a four-transistor static random access memory cell formed on a semiconductor substrate comprising two pass-gate transistors and a flip-flop with two pull-down transistors, characterized by a first pass-­gate transistor adjacent and in series with a first pull-­down transistor, with said first pass-gate transistor and said first pull-down transistor sharing a first common node, and by a second pass-gate transistor adjacent and in series with a second pull-down transistor, with said sec­ ond pass-gate transistor and said second pull-down tran­sistor sharing a second common node, with one pass-gate/­pull-down transistor pair rotated 180° and adjacent the other pass-gate/pull-down transistor pair.

Claim 9

A structure of a four-transistor static random access memory cell formed on a semiconductor substrate comprising two pass-gate transistors and a flip-flop with two pull-down transistors, characterized by a first pass-­gate transistor adjacent and in series with a first pull-­down transistor, with said first pass-gate transistor and said first pull-down transistor sharing a first common node, and by a second pass-gate transistor adjacent and in series with a second pull-down transistor, with said sec­ ond pass-gate transistor and said second pull-down tran­sistor sharing a second common node, with one pass-gate/­pull-down transistor pair rotated 180° and adjacent the other pass-gate/pull-down transistor pair.

Claim 10

The structure of Claim 7 wherein said pull-down transistors each have a gate overlying a gate oxide of a first thickness and said pass-gate transistors each have a gate overlying a gate oxide of a second, independent thickness, and where said gates of said pass-gate transis­tors are formed of a layer which is distinct from the layer of said gates of said pull-down transistors.

Claim 11

The structure of Claim 8 further characterized by said gate of said first pull-down transistor being an integral part of a larger first pull-down gate segment, and by said gate of said second pull-down transistor being an integral part of a larger second pull-down gate seg­ment, with said first pull-down gate segment routed to and positioned over said second common node, and with said second pull-down gate segment routed to and positioned over said first common node.

Claim 12

The structure of Claim 9 further characterized by both of said gates of said pass-gate transistors con­nected together by a connecting segment comprising the same material used to form said gates of said pass-gate transistors, thereby forming a continuous strip which serves as a wordline and wherein said wordline crosses over said first and second pull-down gate segments.

Claim 13

The structure of Claim 9 further characterized by two butting contacts, one providing an electrical connec­tion between said first common node, said second pull-down gate segment and a first resistive load, and another providing an electrical connection between said second common node, said first pull-down gate segment and a second resistive load.

Claim 14

A structure according to any one of the preceding claims wherein said gate layer comprises polysilicon.

Claim 15

A structure according to any one of the claims 1-11 wherein said gate layer comprises a refractory metal.

Claim 16

The structure of claim 13 wherein said refractory metal comprises molybdenum or tungsten.

Claim 17

A structure according to claim 1 or claim 7 wherein said gate layer comprises a refractory metal silicide layer formed on top of a polysilicon layer.

Claim 18

The structure of claim 15 wherein said refractory metal silicide comprises molybdenum, tungsten, titanium or tantalum silicide.

Claim 19

A structure of a four-transistor static random access memory cell formed on a semiconductor substrate comprising two pass-gate transistors and a flip-flop with two pull-down transistors, characterized by (a) a first pass-gate transistor adjacent and in series with a first pull-down transistor, with said first pass-gate transistor and said first pull-down transistor sharing a first common node, and by a second pass-gate transistor adjacent and in series with a second pull-down transistor, with said second pass-gate transistor and said second pull-down transistor sharing a second common node, with one pass-gate/pull-down transistor pair rotated 180° and adjacent the other pass-gate/pull-down transistor pair; (b) said pass-gate transistors each having a gate overlying a gate oxide of a first thickness and said pull-down transistors each having a gate overlying a gate oxide of a second, independent thickness, and where said gates of said pull-down transistors are formed of a poly­silicon layer which is distinct from the polysilicon layer of said gates of said pass-gate transistors; (c) said gate of said first pull-down transistor being an integral part of a larger first pull-down gate segment, and by said gate of said second pull-down tran­sistor being an integral part of a larger second pull-down gate segment, with said first pull-down gate segment routed to and positioned over said second common node, and with said second pull-down gate segment routed to and positioned over said first common node; and (d) two butting contacts, one providing an elec­trical connection between said first common node, said second pull-down gate segment and a first resistive load, and another providing an electrical connection between said second common node, said first pull-down gate segment and a second resistive load.

Claim 20

A structure of a four-transistor static random access memory cell formed on a semiconductor substrate comprising two pass-gate transistors and a flip-flop with two pull-down transistors, characterized by (a) a first pass-gate transistor adjacent and in series with a first pull-down transistor, with said first pass-gate transistor and said first pull-down transistor sharing a first common node, and by a second pass-gate transistor adjacent and in series with a second pull-down transistor, with said second pass-gate transistor and said second pull-down transistor sharing a second common node, with one pass-gate/pull-down transistor pair rotated 180° and adjacent the other pass-gate/pull-down transistor pair; (b) said pass-gate transistors each having a gate overlying a gate oxide of a first thickness and said pull-down transistors each having a gate overlying a gate oxide of a second, independent thickness, and where said gates of said pull-down transistors are formed of a poly­silicon layer which is distinct from the polysilicon layer of said gates of said pass-gate transistors; (c) said gate of said first pull-down transistor being an integral part of a larger first pull-down gate segment, and by said gate of said second pull-down tran­sistor being an integral part of a larger second pull-down gate segment, with said first pull-down gate segment routed to and positioned over said second common node, and with said second pull-down gate segment routed to and positioned over said first common node; and (d) two butting contacts, one providing an elec­trical connection between said first common node, said second pull-down gate segment and a first resistive load, and another providing an electrical connection between said second common node, said first pull-down gate segment and a second resistive load.

Claim 21

The structure of claim 17 further characterised by both of said gates of said pass-gate transistors connected together by a connecting segment comprising the same material used to form said gates of said pass-­gate transistors, thereby forming a continuous strip which serves as a wordline and wherein said wordline crosses over said first and second pull-down gate segments.

Claim 22

A structure according to claim 3, 7 or 17 wherein said gate oxide thickness of said pull-down transistors ranges from about 125 to 250 Å.

Claim 23

The structure of claim 19 wherein said gate oxide thickness ranges from about 125 to 150 Å.

Claim 24

A structure according to claim 3, 7 or 17 wherein said gate oxide thickness of said pass-gate transistors ranges from about 200 to 400 Å.

Claim 25

The structure of claim 21 wherein said gate oxide thickness ranges from about 200 to 250 Å.

Claim 28

The method of claim 23 wherein a symmetrical layout is achieved by placing each pass-gate transistor adjacent a pull-down transistor, in series therewith, with one pass-gate/pull-down transistor pair rotated 180° from the other, thereby permitting a reduction in area required to fabricate said cell.

Claim 29

The method of claim 23 further including forming patterned, appropriately doped, high resistance load regions and low resistance interconnect regions in a polysilicon layer which is distinct from any gate layers.

Claim 30

The method of claim 25 further including forming in one cell two plugs of conductive material, with one plug providing an electrical connection between a first resistive load, a gate segment associated with a second pull-down gate and a first common node shared by a first pull-down transistor and a first pass-gate transistor, and with the other plug providing an electrical connec­tion between a second resistive load, a gate segment associated with a first pull-down gate and a second common node shared by a second pull-down transistor and a second pass-gate transistor.

Claim 31

The method of claim 26 wherein said conductive material consists essentially of doped polysilicon, doped with the same conductivity type as said doped region, or tungsten.