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EP0281349A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Clamp circuits for solid-state imaging devices

Assignee: Sony Corp
•
Filing: 1988-02-29
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Granted: —
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Expires: 2008-02-29
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Abstract

Abstract A clamp circuit for a video camera which has a solid-state imaging element (1) which has an optical black portion (11a) to shield incident light at its peripheral portion, the clamp circuit (4) clamping the signal level of the black portion (11a) as a reference black level of a video signal, comprises a first clamp pulse generator for generating a first clamp pulse (P1) which occurs at least once in a horizontal blanking period and during an interval corresponding to the signal level of the black portion (11a), a second clamp pulse generator for generating a second clamp pulse (P2) which occurs in a vertical blanking period, a detector (5) which receives and compares the signal level of the black portion (11a) with a predetermined reference voltage and when the signal level of the black portion (11a) exceeds the predetermined voltage produces a selection signal, a selector (6) which receives the selection signal and selects the first or the second clamp pulse (P1, P2), a clamp circuit (4) which receives the output of the imaging element (1) and clamps a voltage of the reference black level of the video signal in response to the selected clamp pulse (P1, P2), and a drive circuit (2) for generating vertical and horizontal transfer clocks which are supplied to the imaging element (1) for performing charge transfers, the drive circuit (2) further including a clock hold (26) for holding the vertical transfer clock during at least one horizontal scanning period during the vertical blanking period, the clamp circuit (4) clamping charges generated during the clock hold interval in response to the second clamp signal (P2) to obtain a reference black level signal.

Inventors

  • 👤 Isamu C/O Patents Division Yamamoto
  • 👤 Takashi C/O Patents Division Asaida

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 18:35
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/63; H04N25/633

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 307 words
A clamp circuit for a video camera which has a solid-state imaging element (1) which has an optical black portion (11a) to shield incident light at its peripheral portion, the clamp circuit (4) clamping the signal level of the black portion (11a) as a reference black level of a video signal; the clamp circuit being characterized by: a first clamp pulse generating means for generating a first clamp pulse (P1) which occurs at least once in a horizontal blanking period and during an interval corresponding to said signal level of the black portion (11a); a second clamp pulse generating means for generating a second clamp pulse (P2) which occurs in a vertical blanking period; a detector means (5) which receives and compares the signal level of the black portion (11a) with a predetermined reference voltage and when said signal level of the black portion (11a) exceeds said predetermined voltage produces a selection signal; a selection means (6) which receives said selection signal and selects either one of said first and second clamp pulses (P1, P2) according to said selection signal; a clamp means (4) which receives the output of said imaging element (1) and clamps a voltage of the reference black level of the video signal in response to the clamp pulse (P1, P2) selected by said selection means (6); and a drive means (2) for generating vertical and horizontal transfer clocks which are supplied to said imaging element (1) for performing charge transfers in said imaging element (1), said drive means (2) further including clock hold means (26) for holding the vertical transfer clock during at least one horizontal scanning period during the vertical blanking period; and said clamp circuit (4) clamping charges generated during the clock hold interval in response to said second clamp pulse (P2) so as to obtain a reference black level signal.
Claim 2
Dependent Claim 307 words
A clamp circuit for a video camera which has a solid-state imaging element (1) which has an optical black portion (11a) to shield incident light at its peripheral portion, the clamp circuit (4) clamping the signal level of the black portion (11a) as a reference black level of a video signal; the clamp circuit being characterized by: a first clamp pulse generating means for generating a first clamp pulse (P1) which occurs at least once in a horizontal blanking period and during an interval corresponding to said signal level of the black portion (11a); a second clamp pulse generating means for generating a second clamp pulse (P2) which occurs in a vertical blanking period; a detector means (5) which receives and compares the signal level of the black portion (11a) with a predetermined reference voltage and when said signal level of the black portion (11a) exceeds said predetermined voltage produces a selection signal; a selection means (6) which receives said selection signal and selects either one of said first and second clamp pulses (P1, P2) according to said selection signal; a clamp means (4) which receives the output of said imaging element (1) and clamps a voltage of the reference black level of the video signal in response to the clamp pulse (P1, P2) selected by said selection means (6); and a drive means (2) for generating vertical and horizontal transfer clocks which are supplied to said imaging element (1) for performing charge transfers in said imaging element (1), said drive means (2) further including clock hold means (26) for holding the vertical transfer clock during at least one horizontal scanning period during the vertical blanking period; and said clamp circuit (4) clamping charges generated during the clock hold interval in response to said second clamp pulse (P2) so as to obtain a reference black level signal.
Claim 3
Dependent Claim 41 words
A clamp circuit according to claim 1 wherein the vertical transfer clock comprises 4-phase clock signals and said clock hold means (26) sets at least 3-phase clocks of said 4-phase clock signals in a hold state during one horizontal scanning period.
Claim 4
Dependent Claim 59 words
A clamp circuit according to claim 2 wherein said drive means (2) receives a clock signal which has a frequency of eight times a sampling clock signal, and vertical and horizontal sync signals, and generates the vertical and horizontal transfer clock signals so that they are phase-locked with the sampling clock signal, and the vertical and horizontal sync signals.
Claim 5
Dependent Claim 45 words
A clamp circuit according to claim 3 wherein said clock hold means (26) includes a counter (28), and said counter (28) counts the vertical and horizontal sync signals and generate a signal for holding the vertical transfer clock signal (27) at least once per frame.

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