Patent EP0280276A2 successfully refreshed from Google Patents.
EP0280276A2
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Ultraviolet erasable nonvolatile semiconductor memory device and manufacturing method therefor
Assignee: Toshiba Corp
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Filing: 1988-02-24
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Granted: —
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Expires: 2008-02-24
Abstract
Abstract In a step of forming an interlayer insulation film between memory elements (11-1 and 11-2) in an ultraviolet erasable nonvolatile semiconductor memory device and an upper metal wiring layer (22), a thermal oxide film (17) is formed on a semiconductor substrate (12) and around the stacked gate, and a boron and phosphorus doped oxide film (20) is formed on a phosphorus doped oxide film (19) which is formed on the thermal oxide film (17). Then, a heat treatment is effected to cause the boron and phosphorus doped oxide film (20) to melt and fill the concave portion on the surface of the phosphorus doped oxide film (19).
Inventors
- 👤 Seiichi C/O Patent Division Mori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 21:11
CPC Classifications
H; H10; H10B; H10B41/00; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10P; H10P95/00; H10W20/092; H10W20/098
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
113 words
An ultraviolet erasable nonvolatile semiconductor memory device having a stacked gate structure characterized by comprising a semiconductor substrate of a first conductivity type; at least one memory element (11-1) of stacked gate structure formed on said semiconductor substrate; a thermal oxide film (17) formed on said semiconductor substrate (12) and around said memory element (11-1); a silicon oxide film (19) having phosphorus doped therein and formed on said thermal oxide film (17); and a silicon oxide film (20) having boron and phosphorus doped therein and formed in a concave portion on the surface of said phosphorus doped silicon oxide film (19) which lies in position corresponding to the side of said stacked gate.
Claim 2
Dependent Claim
113 words
An ultraviolet erasable nonvolatile semiconductor memory device having a stacked gate structure characterized by comprising a semiconductor substrate of a first conductivity type; at least one memory element (11-1) of stacked gate structure formed on said semiconductor substrate; a thermal oxide film (17) formed on said semiconductor substrate (12) and around said memory element (11-1); a silicon oxide film (19) having phosphorus doped therein and formed on said thermal oxide film (17); and a silicon oxide film (20) having boron and phosphorus doped therein and formed in a concave portion on the surface of said phosphorus doped silicon oxide film (19) which lies in position corresponding to the side of said stacked gate.
Claim 3
Dependent Claim
110 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said memory element (11-1) includes first and second impurity regions (18-1 and 18-2) of a second conductivity type formed with a predetermined distance therebetween on the main surface of said semiconductor substrate (12) of the first conductivity type, a first insulation film (13-1) formed on that portion of said semiconductor substrate (12) which lies between said first and second impurity regions (18-1 and 18-2), a floating gate (14-1) formed on said first insulation film (13-1), a second insulation film (15-1) formed on said floating gate (14-1), and a control gate (16-1) formed on said second insulation film (15-1).
Claim 4
Dependent Claim
29 words
A nonvolatile semiconductor memory device according to claim 2, characterized in that said first and second insulation films (13-1 and 15-1) are each formed of a silicon oxide film.
Claim 5
Dependent Claim
55 words
A nonvolatile semiconductor memory device according to claim 2, characterized in that said first insulation film (13-1) is formed of a silicon oxide film, and said second insulation film (15-1) is formed of a laminated structure of a first silicon oxide film (15-1A), a silicon nitride film (23-1) and a second silicon oxide film (15-1B).
Claim 6
Dependent Claim
41 words
A nonvolatile semiconductor memory device according to claim 2, characterized in that each of said floating gate (14-1) and control gate (16-1) is formed of a material selected from a group consisting of polysilicon, refractory metal, and silicide of refractory metal.
Claim 7
Dependent Claim
31 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that the concentration of phosphorus in said phosphorus doped silicon oxide film (19) is more than 1 × 10¹⁸ cm⁻³.
Claim 8
Dependent Claim
38 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that each of the concentrations of said boron and phosphorus in said boron and phosphorus doped silicon oxide film (20) is more than 1 × 10¹⁸ cm⁻³.
Claim 9
Dependent Claim
100 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that a contact hole (21) is formed in the concave portion on the surface of said phosphorus doped silicon oxide film (19) on which said boron and phosphorus doped silicon oxide film (20) is formed and in said thermal oxide film (17) lying under said concave portion and characterized by further comprising a wiring layer (22) formed on said phosphorus doped silicon oxide film (19) and said boron and phosphorus doped silicon oxide film (20) to fill said contact hole (21) and electrically connected to said memory element (11-1).
Claim 10
Dependent Claim
49 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that the film thickness (ΔX) on the side wall of said stacked gate of said phosphorus doped silicon oxide film (19) is set larger than the film thickness (ΔY) on said stacked gate and said semiconductor substrate (12).
Claim 11
Independent Claim
118 words
A method for manufacturing an ultraviolet erasable nonvolatile semiconductor memory device of stacked gate structure, characterized by comprising steps of forming at least one memory element (11-1) of stacked gate structure on a semiconductor substrate (12); forming a thermal oxide film (17) on said semiconductor substrate (12) and around said memory element (11-1); forming a phosphorus doped silicon oxide film (19) on said thermal oxide film (17); forming a boron and phosphorus doped silicon oxide film (20) on said phosphorus doped silicon oxide film (19); and effecting heat treatment to cause said boron and phosphorus doped silicon oxide film (20) to melt and fill the concave portion on the surface of said phosphorus doped silicon oxide film (19).
Claim 12
Independent Claim
118 words
A method for manufacturing an ultraviolet erasable nonvolatile semiconductor memory device of stacked gate structure, characterized by comprising steps of forming at least one memory element (11-1) of stacked gate structure on a semiconductor substrate (12); forming a thermal oxide film (17) on said semiconductor substrate (12) and around said memory element (11-1); forming a phosphorus doped silicon oxide film (19) on said thermal oxide film (17); forming a boron and phosphorus doped silicon oxide film (20) on said phosphorus doped silicon oxide film (19); and effecting heat treatment to cause said boron and phosphorus doped silicon oxide film (20) to melt and fill the concave portion on the surface of said phosphorus doped silicon oxide film (19).
Claim 13
Dependent Claim
116 words
A method for manufacturing a semiconductor memory device according to claim 10, characterized in that said memory element (11-1) includes first and second impurity regions (18-1 and 18-2) having a conductivity type opposite to that of said semiconductor substrate (12) and formed with a predetermined distance therebetween on the main surface of said semiconductor substrate (12), a first insulation film (13-1) formed on that portion of said semiconductor substrate (12) which lies between said first and second impurity regions (18-1 and 18-2), a floating gate (14-1) formed on said first insulation film (13-1), a second insulation film (15-1) formed on said floating gate (14-1), and a control gate (16-1) formed on said second insulation film (15-1).
Claim 14
Dependent Claim
32 words
A method for manufacturing a semiconductor memory device according to claim 11, characterized in that said first and second insulation films (13-1 and 15-1) are each formed of a silicon oxide film.
Claim 15
Dependent Claim
58 words
A method for manufacturing a semiconductor memory device according to claim 11, characterized in that said first insulation film (13-1) is formed of a silicon oxide film, and said second insulation film (15-1) is formed of a laminated structure of a first silicon oxide film (15-1A), a silicon nitride film (23-1) and a second silicon oxide film (15-1B).
Claim 16
Dependent Claim
44 words
A method for manufacturing a semiconductor memory device according to claim 11, characterized in that each of said floating gate (14-1) and control gate (16-1) is formed of a material selected from a group consisting of polysilicon, refractory metal, and silicide of refractory metal.
Claim 17
Dependent Claim
34 words
A method for manufacturing a semiconductor memory device according to claim 10, characterized in that the concentration of phosphorus in said phosphorus doped silicon oxide film (19) is more than 1 × 10¹⁸ cm⁻³.
Claim 18
Dependent Claim
41 words
A method for manufacturing a semiconductor memory device according to claim 10, characterized in that each of the concentrations of said boron and phosphorus in said boron and phosphorus doped silicon oxide film (20) is more than 1 × 10¹⁸ cm⁻³.
Claim 19
Dependent Claim
27 words
A method for manufacturing a semiconductor memory device according to claim 10, characterized in that said heat treatment is effected at a temperature of lower than 900°C.
Claim 20
Dependent Claim
127 words
A method for manufacturing a semiconductor memory device according to claim 10, characterized by further comprising steps of forming a contact hole (21) in said phosphorus doped silicon oxide film (19) the concave portion on the surface of which is filled with said boron and phosphorus doped silicon oxide film (20) after said step of effecting heat treatment to cause said boron and phosphorus doped silicon oxide film (20) to melt and fill the concave portion on the surface of said phosphorus doped silicon oxide film (19); forming a wiring layer (22) on said phosphorus doped silicon oxide film (19) and said boron and phosphorus doped silicon oxide film (20); and electrically connecting said wiring layer (22) to said memory element (11-1) through said contact hole (21).
Claim 21
Dependent Claim
109 words
A method for manufacturing a semiconductor memory device according to claim 10, characterized by further comprising a step of making the film thickness (ΔY) on said stacked gate and said semiconductor substrate (12) smaller than the film thickness (ΔX) on the side wall of said stacked gate of said phosphorus doped silicon oxide film (19) by etching back said silicon oxide film (19) by an anisotropic etching process after said step of forming phosphorus doped silicon oxide film (19) on said thermal oxide film (17); and then effecting said step of forming said boron and phosphorus doped silicon oxide film (20) on said phosphorus doped silicon oxide film (19).
References Cited (Backward Citations)
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