Dual port video memory system having semi-synchronous data input and data output

Claim 2

A digital data memory system realized as a single integrated circuit comprising: block oriented data storage means (50) wherein each block has a unique address and includes D data storage elements for storing D data values; a source of system clock signal (CLK); a source of output clock gate signal ( GR); means (23,27) for combining said system clock signal and said output clock gate signal to generate an output clock signal, wherein transitions in said output clock signal are synchronized to transitions in said system clock signal; output buffer means, including: data latching means (52A-52D), coupled to said data storage means for holding D data values provided by said data storage means; and shift register means (54A-54D), having a parallel input port and a serial output port, for receiving D data values, in parallel, from said data latching means, means synchronous with said output clock signal, and for providing said received D data values sequentially, in synchronism with D successive pulses of said output clock signal, via said serial output port; and control means (22,30,31,34,36) coupled to said data storage means and to said output buffer means and responsive to said system clock signal for conditioning said data storage means to provide D data values, in parallel to said output buffer means.

Claim 3

The digital data memory system set forth in claim 1 wherein: said output clock gate signal is an active-low signal; and said combining means includes means for inverting said output clock gate signal to generate a corresponding active-high clock gate signal and means for combining said system clock signal and said active-high clock gate signal according to a logical AND function to generate said output clock signal.

Claim 4

The digital data memory system set forth in claim 2 wherein said shift register means is responsive to the negative-going edges of D successive pulses of said output clock signal for providing, respectively, said received D data values and said shift register means is responsive to the positive-going edge of a pulse of said output clock signal occurring immediately after said D successive pulses for receiving D data values, in parallel, from said data latching means.

Claim 5

A digital data memory system comprising: a source of input data values; block oriented data storage means wherein each block has a unique address and includes D data storage elements for storing D data values; a source of system clock signal; a source of input clock gate signal; a source of output clock gate signal; first combining means for combining said system clock signal and said input clock gate signal to generate an input clock signal, wherein transitions in said input clock signal are synchronized to transitions in said system clock signal; second combining means for combining said system clock signal and said output clock gate signal to generate an output clock signal, wherein transitions in said output clock signal are synchronized to transitions in said system clock signal; input buffer means including: first shift register means, having a serial input port and a parallel output port, for receiving, from said source of input data values, D data values in synchronism with D successive pulses of said input clock signal, and for providing said D received data values in synchronism with said input clock signal, via said parallel output port; and first data latching means, coupled to said first shift register means and to said block oriented data storage means for storing D data values, provided by said first shift register means and for providing said D stored data values, in parallel, to said block oriented data storage means; output buffer means, including: second data latching means, coupled to said block oriented data storage means for holding D data values provided by said block oriented data storage means; and second shift register means, having a parallel input port and a serial output port, for receiving D data values, in parallel, from said second data latching means synchronous with said output clock signal and for providing the D data values received from said second data latching storage means, sequentially in synchronism with D successive pulses of said output clock signal, via said serial output port; and control means, coupled to said input buffer means, to said block oriented data storage means and to said output buffer means and responsive to said system clock signal for conditioning said block oriented data storage means to store D data values from said input buffer means during a first predetermined time interval and to provide D data values to said output buffer means during a second predetermined time interval.

Claim 6

A digital data memory system comprising: a source of input data values; block oriented data storage means wherein each block has a unique address and includes D data storage elements for storing D data values; a source of system clock signal; a source of input clock gate signal; a source of output clock gate signal; first combining means for combining said system clock signal and said input clock gate signal to generate an input clock signal, wherein transitions in said input clock signal are synchronized to transitions in said system clock signal; second combining means for combining said system clock signal and said output clock gate signal to generate an output clock signal, wherein transitions in said output clock signal are synchronized to transitions in said system clock signal; input buffer means including: first shift register means, having a serial input port and a parallel output port, for receiving, from said source of input data values, D data values in synchronism with D successive pulses of said input clock signal, and for providing said D received data values in synchronism with said input clock signal, via said parallel output port; and first data latching means, coupled to said first shift register means and to said block oriented data storage means for storing D data values, provided by said first shift register means and for providing said D stored data values, in parallel, to said block oriented data storage means; output buffer means, including: second data latching means, coupled to said block oriented data storage means for holding D data values provided by said block oriented data storage means; and second shift register means, having a parallel input port and a serial output port, for receiving D data values, in parallel, from said second data latching means synchronous with said output clock signal and for providing the D data values received from said second data latching storage means, sequentially in synchronism with D successive pulses of said output clock signal, via said serial output port; and control means, coupled to said input buffer means, to said block oriented data storage means and to said output buffer means and responsive to said system clock signal for conditioning said block oriented data storage means to store D data values from said input buffer means during a first predetermined time interval and to provide D data values to said output buffer means during a second predetermined time interval.

Claim 7

The digital data memory system set forth in claim 4 wherein: said input clock gate signal and said output clock gate signal are active low signals; and said first combining means includes means for inverting said input clock gate signal to generate a corresponding active-high input clock gate signal, and means for combining said system clock signal and said active-high input clock gate signal according to a logical AND function to generate said input clock signal.

Claim 8

The digital data memory system set forth in claim 4 wherein: said first shift register means is responsive to negative-going edges of D successive pulses of said input clock signal for storing, respectively, said D data values provided by said source of input data values and said first data latching means and is responsive to the positive-going edge of-a pulse of said input clock signal occurring immediately after said D successive pulses for receiving said D stored data values in parallel from said shift register means; and said second shift register means is responsive to negative-going edges of D successive pulses of said output clock signal for providing, respectively, the D data values received from said block oriented data storage means, and is responsive to the positive-going edge of a pulse of said output clock signal occurring immediately after said D successive pulses of said output clock signal, for receiving D data values, in parallel, from said second data latching means.

Claim 9

A video data memory system comprising: a source of input pixel values; block oriented pixel storage means, wherein each block has a unique address and includes D pixel storage elements for storing D pixel values; a source of system clock signal; a source of input clock gate signal; a source of output clock gate signal; first combining means for combining said system clock signal and said input clock gate signal, wherein transitions in said input clock signal are synchronized to transitions in said system clock signal; second combining means for combining said system clock signal and said output clock gate signal to generate an output clock signal, wherein transitions in said output clock signal are synchronized to transitions in said system clock signal; input buffer means including: first shift register means, having a serial input port and a parallel output port, for receiving from said source of input pixel values, D pixel values in synchronism with D successive pulses of said input clock signal, and for providing said received D data values, in parallel, via said parallel output port; and first pixel latching means, coupled to said first shift register means and to said block oriented pixel storage means and responsive to a first control signal for storing D pixel values, provided by said first shift register means and for providing said D stored pixel values, in parallel, to said block oriented pixel storage means; output buffer means, including: second pixel latching means, coupled to said block oriented pixel storage means for holding D data values provided by said block oriented pixel storage means; and second shift register means, having a parallel input port and a serial output port, responsive to a second control signal for storing D data values, in parallel, from said second pixel latching means and responsive to D successive pulses of said output clock signal for providing, respectively, the D stored pixel values; and control means, coupled to said input buffer means, to said block oriented pixel storage means and to said output buffer means, responsive to said system clock signal for conditioning said block oriented pixel storage means to store D pixel values from said input buffer means during a first predetermined time interval and to provide data values to said output buffer means during a second predetermined time interval and responsive to said input clock signal and to said output clock signal for generating said first and second control signals, respectively.

Claim 10

A video data memory system comprising: a source of input pixel values; block oriented pixel storage means, wherein each block has a unique address and includes D pixel storage elements for storing D pixel values; a source of system clock signal; a source of input clock gate signal; a source of output clock gate signal; first combining means for combining said system clock signal and said input clock gate signal, wherein transitions in said input clock signal are synchronized to transitions in said system clock signal; second combining means for combining said system clock signal and said output clock gate signal to generate an output clock signal, wherein transitions in said output clock signal are synchronized to transitions in said system clock signal; input buffer means including: first shift register means, having a serial input port and a parallel output port, for receiving from said source of input pixel values, D pixel values in synchronism with D successive pulses of said input clock signal, and for providing said received D data values, in parallel, via said parallel output port; and first pixel latching means, coupled to said first shift register means and to said block oriented pixel storage means and responsive to a first control signal for storing D pixel values, provided by said first shift register means and for providing said D stored pixel values, in parallel, to said block oriented pixel storage means; output buffer means, including: second pixel latching means, coupled to said block oriented pixel storage means for holding D data values provided by said block oriented pixel storage means; and second shift register means, having a parallel input port and a serial output port, responsive to a second control signal for storing D data values, in parallel, from said second pixel latching means and responsive to D successive pulses of said output clock signal for providing, respectively, the D stored pixel values; and control means, coupled to said input buffer means, to said block oriented pixel storage means and to said output buffer means, responsive to said system clock signal for conditioning said block oriented pixel storage means to store D pixel values from said input buffer means during a first predetermined time interval and to provide data values to said output buffer means during a second predetermined time interval and responsive to said input clock signal and to said output clock signal for generating said first and second control signals, respectively.