Data input circuit having latch circuit

Claim 2

An input circuit comprising at least one input terminal supplied with input data, a latch circuit having at least one input node and at least one output node and latching data at said input node therein in response to a latch pulse, means for coupling said input terminal to said input node of said latch circuit, a timing circuit generating said latch pulse in a predetermined cycle, at least one output terminal, a buffer circuit receiving a read request signal and coupling said output node of said latch circuit to said output terminal when said read request signal takes an active level, and means coupled to said timing circuit for inhibiting said latch pulse from being generating until said read request signal changes to an inactive level.

Claim 3

The circuit as claimed in claim 1, wherein said timing circuit includes a divider supplied with a clock signal, said divider dividing said clock signal to generate said latch pulse, said inhibiting means including gate means for preventing said clock signal from being supplied to said divider when said read request signal takes said active level.

Claim 4

The circuit as claimed in claim 1, wherein said timing circuit includes means for dividing a clock signal to produce a control signal and means for responsive to said control signal for creating said latch pulse, said inhibiting means includes means for inactivating said creating means when said read request signal takes said active level and means for storing the control signal which is produced by said dividing means while said read request signal takes said active level, said storing means outputting the stored control signal to said creating means after said read request signal changes to said inactive level.

Claim 5

An input circuit comprising a set of input terminals supplied with input data consisting of a plurality of bits, means for generating a reference voltage, a comparator circuit comparing a level of each bit of said input data with said reference voltage, a timing circuit cyclically generating a latch-enable pulse, a latch circuit latching data derived from said comparator circuit in response to said latch-enable pulse, a set of output terminals, a buffer circuit receiving a read signal and transferring data latched in said latch circuit to said set of output terminals when said read signal takes an active level, and means coupled to said timing circuit for changing a generation cycle of said latch-enable pulse such that said latch-enable pulse is generated after said read signal changes to an inactive level.

Claim 6

An input circuit comprising a set of input terminals supplied with input data consisting of a plurality of bits, means for generating a reference voltage, a comparator circuit comparing a level of each bit of said input data with said reference voltage, a timing circuit cyclically generating a latch-enable pulse, a latch circuit latching data derived from said comparator circuit in response to said latch-enable pulse, a set of output terminals, a buffer circuit receiving a read signal and transferring data latched in said latch circuit to said set of output terminals when said read signal takes an active level, and means coupled to said timing circuit for changing a generation cycle of said latch-enable pulse such that said latch-enable pulse is generated after said read signal changes to an inactive level.

Claim 7

The input circuit as claimed in claim 4, further comprising a set of address terminals supplied with address information, said changing means decoding said address information and changing the generation cycle of said latch-enable pulse when said address information represents that said input circuit is to be selected.

Claim 8

The input circuit as claimed in claim 1, further comprising a sample-hold circuit inserted between said set of input terminals and said comparison circuit, said sample-­hold circuit sampling and holding the level of each bit of said input data.

Claim 9

The input circuit as claimed in claim 6, wherein said timing circuit further generates an operating control signal which cyclically changes between a first logic level and a second logic level, said sample-hold circuit sampling the level of each bit of said input data when said operating control signal takes said first logic level and holding the level of each bit of said input data when said operating control signal takes said second logic level.

Claim 10

The input circuit as claimed in claim 7, wherein said latch-enable pulse is generated just before said operating control signal changes from said second logic level to said first logic level.

Claim 11

The input circuit as claimed in claim 4, wherein said reference voltage generating means includes a potential source generating a plurality of reference potentials and a multiplexer selecting one of said reference potentials and outputting the selected reference potential as said reference voltage.

Claim 12

A data processing equipment comprising a central processing unit; an input port supplied with input data; a data bus interconnecting said central processing unit and said input port; and an address bus interconnecting said central processing unit and said input port; said central processing unit outputting address data to said address bus to access said input port and supplying a read signal to said input port to introduce said input data; said input port including at least one input terminal supplied with said input data, a timing circuit cyclically generating a latch pulse, a latch circuit latching said input data in response to said latch pulse, a buffer circuit transferring data latched in said latch circuit to said data bus in response to said read signal, a decoder decoding said address data and producing a decoded signal when said address data has information representing that said central processing unit accesses said input port, and means responsive to said decoded signal for delaying generation of said latch pulse such that said latch pulse is generated after said central processing unit stops to supplying said read signal.

Claim 13

A data processing equipment comprising a central processing unit; an input port supplied with input data; a data bus interconnecting said central processing unit and said input port; and an address bus interconnecting said central processing unit and said input port; said central processing unit outputting address data to said address bus to access said input port and supplying a read signal to said input port to introduce said input data; said input port including at least one input terminal supplied with said input data, a timing circuit cyclically generating a latch pulse, a latch circuit latching said input data in response to said latch pulse, a buffer circuit transferring data latched in said latch circuit to said data bus in response to said read signal, a decoder decoding said address data and producing a decoded signal when said address data has information representing that said central processing unit accesses said input port, and means responsive to said decoded signal for delaying generation of said latch pulse such that said latch pulse is generated after said central processing unit stops to supplying said read signal.

Claim 14

The data processing equipment as claimed in claim 10, wherein said input port further includes a comparator inserted between said at least one input terminal and said latch circuit and means for generating a reference voltage, said comparator comparing a level of said input data with said reference voltage to produce logic data, said latch circuit latching the logic data produced by said comparator.