Circuit for computing the quantized coefficient discrete cosine transform of digital signal samples

Claim 2

Circuit as in claim 1, characterized in that for N=16 said first calculating unit (ERM) comprises: - a first and a second multiplexer (MX1, MX2) which at a first input receive output (3) of said first adder (SOM1) and at a second input receive output of a first register (RG7); - first and second shifting units (SH1, SH2) which receive outputs of the first and second multiplexer respectively; - a third adder/subtracter (SMST3) which receives outputs of said first and second shifting units, for adding or subtracting the output of the second shifting units (SH2) to or from that of the first shifting units (SH1), and whose output supplies said first register (RG7) and is the output of said first calculating unit (ERM); in addition, characterized in that said second calculating unit (ORM) comprises: - a third and fourth multiplexers (MX3, MX4) which at a first input receive output (4) of said first subtracter (SOT1), said third multiplexer receiving at a second input the output of a second register (RG8), said fourth multiplexer also receiving the outputs of a third and fourth register (RG9, RG10) at a third and fourth input; - third and fourth shifting units (SH3, SH4) which receive outputs of the third and fourth multiplexers respectively; - a fourth adder/subtracter (SMST4) which receives outputs of said third and fourth shifting units, for adding or subtracting the output of the third shifting units (SH3) to or from that of the fourth shifting units (SH4) and whose output supplies said second, third and fourth registers (RG8, RG9, RG10) and is the output of said second calculating unit (ORM), said first, second, third and fourth registers being used for temporary storage of said previous partial products.

Claim 3

Circuit as in claim 2, characterized in that said first control signals (7) generated by said first addressing units (ADR2) cause the following succession of operations to be performed by said first and second calculating units (ERM, ORM): for the first partial product, the first, second, third and fourth multiplexers (MX1, MX2, MX3, MX4) are switched on the first input, the first, second, third and fourth shifting units (SH1, SH2, SH3, SH4) shift respectively by four, one, zero and three positions to the left, in the direction of multipliactions by powers of two, the third and fourth adder/subtracter (SMST3, SMST4) execute the sum, said first and second registers (RG7, RG8) memorize the input datum; for the second partial product the first, second, third and fourth multiplexers are switched respectively on the second, first, second, first input, the first, second, third and fourth shifting units shift respectively by one, zero, one and three positions to the left, the third and fourth adder/subtracters execute the sum and the difference respectively, said third register (RG9) memorizes the input data; for the third partial product the first, second, third and fourth multiplexers are switched on the second, first, second and third input, the first, second, third and fourth shifting units shift by zero, five, zero and one positions to the left, the third adder/subtracter executes the sum and the fourth the difference, said first and fourth registers (RG7, RG10) memorize the input data; for the fourth partial product the first, second and fourth multiplexers are switched on the first input, the third multiplexer on the second input, the first, second, third and fourth shifting units shift by five, five, three and one position to the left, the third adder/subtracter executes the sum and the fourth the difference; for the fifth partial product the first and second multiplexers are switched on the second input, the third and fourth on the first input, the first shifting unit shifts by one position to the right in the direction of division by powers of two, the third and fourth shifting units shift by six and four positions to the left, the third and fourth adder/subtracters execute the sum, the second register memorizes the input datum; for the sixth partial product the first, second, third and fourth multiplexers are switched on the second, first, second and third inputs, the first, second and fourth shifting units shift by one, four and one position to the left, the third shifting unit shifts by four positions to the right, the third adder/subtracter executes the difference and the fourth the sum; for the seventh partial product the first, second, third and fourth multiplexers are switched on the second, first, first and fourth inputs, the first shifting unit shifts by one position to the right, the second and fourth shifting units shift by six and one position to the left, the third and fourth adder/subtracters execute the sum; for the eighth partial product, the first, second and third multiplexers are switched on the first input, the fourth on the third input, the first, second and third shifting units shift by five, five and six positions to the left, the third and fourth adder/subtracters execute the sum.

Claim 4

Circuit as in claim 1, characterized in that for N=16 said first and second calculating units (ERM, ORM) include six and eight, respectively, adders or subtracters which produce an equal number of partial products through suitable adjustments of their two inputs, six and eight registers which memorize the results thereof, a further register (RG17) connected to the input of said first calculating unit (ERM) and multiplexers which receive the outputs of said registers, said first control signals (7) generated by said addressing unit (ADR2) determining only the connection sequence of multiplexer inputs with outputs.

Claim 5

Circuit as in claim 4, characterized in that said first calculating unit (ERM) features the following interconnection between said adders or subtracters, with the intercalation of said registers: to a second adder (SM1) is applied the output of said first adder (SOM1) shifted to the left by one and four positions; to a third adder (SM2) are brought the outputs of said first adder, shifted by five positions to the left, and of said second adder; to a second subtracter (ST1) are brought the outputs of the second adder, shifted by one position to the left, and of the first adder; to a third subtracter (ST2) are brought the outputs of the first adder, shifted by four positions to the left, and of the third adder, shifted by one position to the left; to a fourth adder (SM3) are connected the outputs of the first adder, shifted by six positions to the left, and of the third adder, shifted by one position to the right; to a fifth adder (SM4) is applied the output of the third adder shifted by one position to the right at one input; said further register (RG17) receives the output of the first adder shifted by six positions to the left; in addition, characterized in that said second calculating unit (ORM) features the following interconnection between said adders and subtracters, with the intercalation of said registers: to a sixth and seventh adder (SM5, SM6) is applied the output of the first subtracter (SOT1) respectively shifted by six and four positions to the left and by three and zero positions to the left; to an eighth adder (SM7) are brought the outputs of the first subtracter, shifted by three positions to the left, and of the seventh adder, shifted by one position to the left; to a fourth subtracter (ST3) are brought the outputs of the first subtracter (SOT1), shifted by one position to the left, and of the seventh adder, shifted by three positions to the left; to a fifth subtracter (ST4) are applied the outputs of the seventh adder and the outputs of the eighth adder, shifted by one position to the left; to a ninth adder (SM8) are brought the outputs of the first subtracter, shifted by six positions to the left, and of the eighth adder; to a tenth adder (SM9) are applied the outputs of the sixth adder, shifted by four positions to the right, and of the eighth adder, shifted by one position to the left; to an eleventh adder (SM10) are brought the output of the first subtracter, and the output of the fifth subtracter, shifted by one position to the left; said output multiplexers (MX5, MX6) connecting inputs to outputs (5, 6) in the following order: for the first partial product, the outputs of the second and seventh adder (SM1, SM6); for the second partial product, the outputs of the second subtracter (ST1) and the eighth adder (SM7); for the third partial product, the outputs of the third adder (SM2) and the fifth subtracter (ST4); for the fourth partial product, the outputs of the further register (RG17) and the fourth subtracter (ST3); for the fifth partial product, the outputs of the fifth and sixth adder (SM4, SM5); for the sixth partial product, the outputs of the third subtracter (ST2) and the tenth adder (SM9); for the seventh partial product, the outputs of the fourth and eleventh adder (SM3, SM10); for the eighth partial product, the outputs of the further register (RG17) and the ninth adder (SM8).

Claim 6

Circuit as in claim 1, characterized in that for N=8 said first calculating unit (ERM) includes: - a fifth and a sixth multiplexer (MX7, MX8) which receive at a first input the output (4) of said first adder (SOM1), at a second input the output (20) of a fifth register (RG27); said sixth multiplexer receiving at a third input the output (21) of a sixth register (RG28) shifted by one position to the left, and with the outputs applied to its first and second inputs shifted by three positions to the left; - a fifth shifting unit (SH5) which receives the output of the fifth multiplexer (MX7); - a sixth subtracter (SMST5) which subtracts the output of the fifth shifting unit from that of the sixth multiplexer, and whose output (5) supplies said fifth and sixth registers and is the output of said first calculating unit; in addition, characterized in that said second calculating unit (ORM) includes: - a seventh and an eighth multiplexer (MX9, MX10) which receive at a first input the output (4) of said first subtracter (SOT1), and at a second input the outputs (22, 23) of a seventh and an eighth register (RG29, RG30) respectively; - sixth and seventh shifting units (SH6, SH7) which receive respectively the outputs of said seventh and eighth multiplexers (MX9, MX10); - a sixth adder/subtracter (SMST6) which receives the outputs of said sixth and seventh shifting units, for adding or subtracting the output of the sixth shifting unit to or from that of the seventh, and whose output (6) supplies said seventh and eighth registers (RG29, RG30) and is the output of said second calculating unit; said fifth, sixth, seventh, eighth registers being used for temporary storage of said previous partial products.

Claim 7

Circuit as in claim 6, characterized in that said first control signals (7) generated by said addressing units (ADR2) cause the following succession of operations on the part of said first and second calculating units (ERM, ORM): for the first partial product, the fifth, sixth, seventh and eighth multiplexers (MX7, MX8, MX9, MX10) are switched on the first input (3, 4), the fifth, sixth, and seventh shifting units (SH5, SH6, SH7) shift by zero, zero and three positions to the left, the sixth adder/subtracter preforms subtraction, the fifth and seventh registers (RG27, RG29) memorize the input datum; for the second partial product, the fifth, sixth, seventh multiplexers are switched on the second input, the eighth multiplexer on the first input, the fifth, sixth and seventh shifting units shift by zero, zero and five positions, the sixth adder/subtracter performs subtraction, the sixth and eihth registers (RG28, RG30) memorize the input datum; for the third partial product, the fifth, sixth, seventh and eighth multiplexers are swithched respectively on the second, third, second and fifth inputs, the fifth, sixth and seventh shifting units shift by zero, zero and six positions to the left, the sixth adder/subtracter executes the sum; for the fourth partial product, the fifth, sixth, seventh and eighth multiplexers are switched respectively on the second, third, second and second inputs, the fifth, sixth and seventh shifting units shift by zero, three and one position to the left, the sixth adder/subtracter executes the sum, the seventh register memorizes the input datum; for the fifth partial product, the fifth, sixth, seventh and eighth multiplexers are switched on the first, third, first and first input, the fifth, sixth and seventh shifting units shifts by six, one and seven positions to the left, and the sixth adder/subtracter performs subtraction.

Claim 8

Circuit as in claim 1, charcaterized in that, for N=8, said first and second calculating units (ERM, ORM) include respectively four and five adders of subtracters which produce an equal number of partial products through suitable adjustments of their two inputs, four and five registers which memorize the results thereof, and an output multiplexer which receives the outputs of said registers, said first control signals (7) generated by said addressing unit (ADR2) determining only the connection sequence of multiplexer inputs with outputs.

Claim 9

Circuit as in claim 8, characterized in that said first calculating unit (ERM) features the following interconnection between said adders or subtracters, with the intercalation of said registers: to a seventh subtracter (ST6) is applied the output of the first adder (SOM1) shifted by three positions to the left at one input; to an eighth subtracter (ST7) is applied the output of the seventh subtracter shifted at an input by three positions; to a ninth subtracter (ST8) are applied the outputs of the seventh subtracter, and of the eighth subtracter shifted by one position to the left; to a tenth subtracter (ST9) are brought the outputs of the first adder, shifted by six positions to the left, and of the ninth subtracter shifted by one position to the left; and characterized also in that said second calculating unit (ORM) features the following interconnection between said adders or subtracters, with the intercalation of said registers: to an eleventh and twelfth subtracter (ST10, ST11) is applied the output of said first subtracter (SOT1) respectively shifted by three, zero, seven and one position to the left; to a thirteenth subtracter (ST12) are applied the outputs of the first adder, shifted by five positions to the left, and the eleventh subtracter; to a twelfth adder (SM12) are applied the outputs of the first subtracter, shifted by six positions to the left, and of the eleventh subtracter; to a thirteenth adder (SM13) are applied the outputs of the eleventh subtracter shifted by three positions to the left, and of the thirteenth subtracter, shifted by one position to the left; output multiplexers (MX11, MX12) connecting inputs to outputs (5, 6) in the following order: for the first partial product, the outputs of the eighth and the thirteenth subtracters (St7, ST12); for the second partial product, the outputs of the ninth subtracter (ST8) and the twelfth adder (SM12); for the third partial product, the outputs of the ninth subtracter (ST8) and the thirteenth adder (SM13); for the fourth partial product, the outputs of the tenth and twelfth subtracter (ST9, ST11).

Claim 10

Circuit as in any of claims 1 to 9, characterized in that said first addressing unit (ADR2) supply to outside a data-ready (DRT) signal at the beginning of the operations relating to the N2-1 index column; on the basis of said signal, the partial results R(k) at the outputs of said first and second adder/subtracters (SMST1, SMST2) are available at outputs (12, 13) as components of a transformed F(k) sample vector.

Claim 11

Circuit as in any of claims 1 to 10, characterized in that said first addressing unit (ADR2) supply, at the end of calculations relating to the index N2-1 column, addresses to said first and second accumulation memories (MEM2, MEM3) for sequential reading and forwarding to the outputs of R(k) partial results, there memorized, as components of a transformed F(k) sample vector.

Claim 12

Circuit as in any of claims 1 to 11, characterized in that the data at the outputs of said first adder (SOM1), first subtracter (SOT1), first and second calculating units (ERM, ORM) and first and second accumulation memories (MEM2, MEM3) are synchronized by registers (RG1, ..., RG6).

Claim 13

Circuit as in claim 2 or 3 or 6 or 7, characterized in that said shifting units (SH1, ... SH7) consists of barrel shifters.

Claim 14

Circuit for computing the two-dimensional discrete cosine transform using circuits as in any of the preceding claims, characterized in that it includes a first of said circuits (DCT1) followed by a matrix-structured intermediate memory (MEM4) and by a second of such circuits (DCT2), and second addressing units (ADR3) for said intermediate memory which determine writing of N vectors of transformed F(k) samples, calculated by the first circuit, and reading in a direction orthogonal to that of writing, of N vectors of f(j) samples to be transformed, each consisting for the (k-n)th component of said F(k) vectors present in said intermediate memory, for forwarding to the second circuit (DCT2).