Switched capacitor circuit

Claim 2

A switched capacitor circuit having : an integrating capacitor (4), an operational amplifier (1) having a differential stage (61, 62, 63, 64, 65), a gain stage (66, 67) for amplifying a single-ended output signal from said differential stage, and a frequency compensation buffer (68, 69), said operational amplifier having an output end (2) and an inverting input end (3) between which said integrating capacitor (4) is connected, a sampling circuit having an analog switch (6, 7, 8, 9) and a sampling capacitor (5) connected between a signal input end (10) and said inverting input end (3) of said operational amplifier (1), and a switch control circuit (11) for controlling said analog switch (6, 7, 8, 9) characterized in that it comprises : an operating point stabilizing circuit (73) for detecting a variation component of the power supply, for supplying a detected variation component having the same phase as a phase of the power supply voltage (V DD ) to said gain stage (66, 67) of said operational amplifier, and for stabilizing an operation point of said gain stage.

Claim 3

A circuit according to claim 1, wherein said operating point stabilizing bias circuit comprises : a voltage variation component detector having a series circuit of a high resistive element (104) and a capacitive element (105, 114), said high resistive element having one end connected to a voltage source which is free from the influence of the variation in the power supply voltage, and said capacitive element having one end connected to the power supply voltage (V DD ) and a connection such as to add the detected variation component to a bias voltage of a transistor for determining an operating current of said frequency compensation buffer, whereby the voltage variation component is applied to a gate of a transistor of said gain stage through said frequency compensating buffer and a frequency compensation capacitor, thereby keeping a gate-source voltage of said transistor constant.

Claim 4

A circuit according to claim 1, characterized in that it further comprises : a substrate bias circuit (140, 141, 142, 143, 144) for detecting a leakage component of the variation in the power supply voltage which is transmitted to a signal line through a parasitic capacitance of a transis­tor of said analog switch, for producing an inverted voltage (V PWell ) having a phase opposite to a phase of the leakage component, for applying the inverted voltage to a substrate of said analog switch, and for cancelling the leakage component.

Claim 5

A circuit according to claim 3, having said analog switch comprises a P-channel MOS transistor and an N-channel MOS transistor, which is isolated from a subs­trate of said P-channel MOS transistor by a P-type element isolation diffusion layer (P-well); and said substrate bias circuit comprises : a dummy switch (140) which has the same arrangement as said analog switch, a detector amplifier (141) for detecting the leakage component of the variation in the power supply voltage which appears at an output end of said dummy switch (140) through a parasitic capacitance of said dummy switch ; a level shifter for converting a DC level of an output signal from said (147) detector amplifier (141) to a level of a P-well voltage required for a switching operation of said analog switch ; a feedback circuit for AC coupled feed back of an output signal from said level shifter (142) to said P-type element isolation diffusion layer of said dummy switch ; and a connector circuit for applying the inverted voltage to said P-type element isolation diffusion layer of said analog switch, the inverted voltage being obtained at an output end (146) of said level shifter (142).