Patent EP0273728A2 successfully refreshed from Google Patents.
EP0273728A2
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Semiconductor memory device and method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1987-12-23
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Granted: —
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Expires: 2007-12-23
Abstract
Abstract The invention provides a semiconductor memory device and a method of manufacturing the same including a semiconductor substrate (21) of a first conductivity type, comprising, a gate insulating film (24) on a channel region of the semiconductor substrate (21), a floating gate (25) on the gate insulating film (24), a floating gate insulating film on the floating gate (25), a control gate (26) on the floating gate insulating film, first and second impurity regions (22, 23) of a second conductivity type in the semiconductor substrate (21) and being adjacent to the gate insulating film (24), a third impurity region (221, 231) of the second conductivity type more lightly doped than the first and second impurity regions (22, 23), being adjacent to the channel region, and a fourth impurity region (222, 232) of the second conductivity type more highly doped than the third impurity region (221, 231) and more lightly doped than the first and second impurity regions (22, 23) in the surface region of the third impurity region.
Inventors
- 👤 Masaki Patent Division Sato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 22:11
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/44; H10B41/48; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
162 words
A semiconductor memory device including a semiconductor substrate (21) of a first conductivity type, comprising: a gate insulating film (24) on a channel region of the semiconductor substrate (21); a floating gate (25) on the gate insulating film (24); a floating gate insulating film on the floating gate (25); a control gate (26) on the floating gate insulating film; and first and second impurity regions (22, 23) of a second conductivity type in the semiconductor substrate (21) and being adjacent to the gate insulating film (24); characterised by a third impurity region (221, 231) of the second conductivity type more lightly doped than the first and second impurity regions (22, 23), being adjacent to the channel region; and a fourth impurity region (222, 232) of the second conductivity type more highly doped than the third impurity region (221, 231) and more lightly doped than the first and second impurity regions (22, 23), being in the surface region of the third impurity region.
Claim 2
Dependent Claim
162 words
A semiconductor memory device including a semiconductor substrate (21) of a first conductivity type, comprising: a gate insulating film (24) on a channel region of the semiconductor substrate (21); a floating gate (25) on the gate insulating film (24); a floating gate insulating film on the floating gate (25); a control gate (26) on the floating gate insulating film; and first and second impurity regions (22, 23) of a second conductivity type in the semiconductor substrate (21) and being adjacent to the gate insulating film (24); characterised by a third impurity region (221, 231) of the second conductivity type more lightly doped than the first and second impurity regions (22, 23), being adjacent to the channel region; and a fourth impurity region (222, 232) of the second conductivity type more highly doped than the third impurity region (221, 231) and more lightly doped than the first and second impurity regions (22, 23), being in the surface region of the third impurity region.
Claim 3
Dependent Claim
53 words
A semiconductor memory device as claimed in claim 1, further characterised in that the semiconductor memory device comprises a fifth impurity region (18) of the first conductivity type more highly doped than the semiconductor substrate (1) and being deeper from the surface of the semiconductor substrate (1) than the third impurity region (14).
Claim 4
Independent Claim
143 words
A method of manufacturing a semiconductor memory device having a semiconductor substrate (21) of a first conductivity type comprising characterised by the steps of: (a) forming a gate insulation layer (24) on the semiconductor substrate (21); (b) depositing a first gate pattern on the gate insulation layer (25) to form a floating gate (25); (c) implanting ions of the second conductivity type into the substrate (21), using the gate pattern as a mask; (d) implanting ions of the second conductivity type in a dose different from the ion implanting of the step (c) into the substrate (21) using the gate pattern as a mask; (e) forming a silicon oxide film on the side face portions of the floating gate (25); and (f) implanting ions of the second conductivity type into the substrate using the gate pattern as a mask after the step (e).
Claim 5
Independent Claim
143 words
A method of manufacturing a semiconductor memory device having a semiconductor substrate (21) of a first conductivity type comprising characterised by the steps of: (a) forming a gate insulation layer (24) on the semiconductor substrate (21); (b) depositing a first gate pattern on the gate insulation layer (25) to form a floating gate (25); (c) implanting ions of the second conductivity type into the substrate (21), using the gate pattern as a mask; (d) implanting ions of the second conductivity type in a dose different from the ion implanting of the step (c) into the substrate (21) using the gate pattern as a mask; (e) forming a silicon oxide film on the side face portions of the floating gate (25); and (f) implanting ions of the second conductivity type into the substrate using the gate pattern as a mask after the step (e).
Claim 6
Dependent Claim
36 words
A method of manufacturing a semiconductor memory device as claimed in claim 3, further characterised in that ions of the first conductivity type are implanted into the substrate (21), using the gate pattern as a mask.
Claim 7
Dependent Claim
37 words
A method of manufacturing a semiconductor memory device as claimed in claim 3 or claim 4, further characterised in that the amount of ion implanting of the step (c) is higher than that of the step (d).
Claim 8
Dependent Claim
56 words
A method of manufacturing a semiconductor memory device as claimed in claim 4 or claim 5, further characterised in that boron ions are implanted in the first conductivity type ions implanting step, arsenic ions are implanted in the step (C), arsenic ions and phosphorus ions are implanted in the step (d) and the step (f), respectively.
References Cited (Backward Citations)
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