Loosely coupled pipeline processor

Claim 2

A central processing unit comprising: (a) an instruction decoder for decoding an instruction to generate first control information, second control information, and third control information; (b) an operand address computation unit for computing an operand address in accordance with said first control information; (c) an operand pre-fetch unit for fetching and queueing a memory operand in accordance with said operand address, and for outputting said memory operand and a first signal representing that said memory operand has been queued therein; (d) a control information buffer for queueing and outputting said second control information, and for outputting a second signal representing that said second control informatoin is valid in accordance with said first signal and said third control information; and (e) an arithmetic unit for receiving said second signal and for outputting a third signal representing that said arithmetic unit requires said second control information queued in said control information buffer thereby executing an operation in accordance with said second control information and said memory operand.

Claim 3

A central processing unit as claimed in Claim 1, wherein said operand pre-fetch unit includes: (i) an operand reader for reading said memory operand; (ii) a first storage means for queueing said memory operand to send said memory operand to said arithmetic unit; and (iii) a first control unit for sending said first signal to said control information buffer when said memory operand is queued in said first storage means.

Claim 4

A central processing unit as claimed in Claim 1, wherein said control information buffer includes: (i) a second storage means for queueing said second control information to send said second control information to said arithmetic unit; (ii) a third storage means for queueing and outputting said third control information; (iii) a second control unit for outputting a fourth signal representing that said second control information has been queued in said second storage means, and for receiving said third signal; and (iv) a synchronizing circuit means responsive to said first and fourth signals and said third control information from said third storage means for outputting said second signal.

Claim 5

A central processing unit as claimed in Claim 1, wherein said arithmetic unit includes: (i) an arithmetic logic unit; (ii) a register bank having general purpose registers; and (iii) a third control unit for receiving said second signal and for outputting said third signal to said control information buffer.

Claim 6

A central processing unit comprising: (a) an instruction decoder for decoding an instruction to generate first control information, second control information, and third control information; (b) an operand address computation unit for computing an operand address in accordance with said first control information;. (c) an operand pre-fetch unit for fetching and queueing a memory operand in accordance with said operand address, and for outputting said memory operand and a first signal representing that said memory operand has been queued therein; (d) a control information buffer for queueing and outputting said second control information and said third control information, and for outputting a second signal representing that said second control information has been queued therein; and (e) an arithmetic unit for receiving said first and said second signals and said third control information, and for outputting a third signal representing that said arithmetic unit requires said second control information from said control information buffer thereby executing an operation in accordance with said second control information and said memory operand.

Claim 7

A central processing unit comprising: (a) an instruction decoder for decoding an instruction to generate first control information, second control information, and third control information; (b) an operand address computation unit for computing an operand address in accordance with said first control information;. (c) an operand pre-fetch unit for fetching and queueing a memory operand in accordance with said operand address, and for outputting said memory operand and a first signal representing that said memory operand has been queued therein; (d) a control information buffer for queueing and outputting said second control information and said third control information, and for outputting a second signal representing that said second control information has been queued therein; and (e) an arithmetic unit for receiving said first and said second signals and said third control information, and for outputting a third signal representing that said arithmetic unit requires said second control information from said control information buffer thereby executing an operation in accordance with said second control information and said memory operand.

Claim 8

A central processing unit as claimed in Claim 5, wherein said operand pre-fetch unit includes: (i) an operand reader for reading said memory operand; (ii) a first storage means for queueing said memory operand to send said memory operand to said arithmetic unit; and (iii) a first control unit for sending said first signal to said arithmetic unit when said memory operand is queued in said first storage means.

Claim 9

A central processing unit as claimed in Claim 5, wherein said control information buffer includes: (i) a second storage means for queueing said second control information to send said second control information to said arithmetic unit; (ii) a third storage means for queueing and outputting said third control information; and (iii) a second control unit for outputting said second signal, and for receiving said third signal.

Claim 10

A central processing unit as claimed in Claim 5, wherein said arithmetic unit includes: (i) an arithmetic logic unit; (ii) a register bank having general purpose registers; (iii) a third control unit for receiving said second signal and for outputting said third signal and a fourth signal representing that said second signal has been received, and for receiving a fifth signal representing that said second control information is valid; and (iv) a synchronizing circuit means responsive to said first and fourth signals and said third control information from said control information buffer for outputting said fifth signal.

Claim 11

A central processing unit comprising: (a) an instruction decoder for decoding an instruction to generate first control information, second control information, and third control information; (b) an operand address computation unit for computing an operand address in accordance with said first control information; (c) an operand pre-fetch unit for fetching and queueing a memory operand in accordance with said operand address, and for outputting said memory operand and a first signal representing that said memory operand has been queued therein; (d) a control information buffer for queueing and outputting said second control information and said third control information, and for outputting a second signal representing that said second control informatoin and said third control information are valid; and (e) an arithmetic unit for receiving said second signal and for outputting a third signal representing that said arithmetic unit requires said second control information and said third control information queued in said control information buffer thereby executing an operation in accordance with said second control information, said third control information, and said memory operand.

Claim 12

A central processing unit comprising: (a) an instruction decoder for decoding an instruction to generate first control information, second control information, and third control information; (b) an operand address computation unit for computing an operand address in accordance with said first control information; (c) an operand pre-fetch unit for fetching and queueing a memory operand in accordance with said operand address, and for outputting said memory operand and a first signal representing that said memory operand has been queued therein; (d) a control information buffer for queueing and outputting said second control information and said third control information, and for outputting a second signal representing that said second control informatoin and said third control information are valid; and (e) an arithmetic unit for receiving said second signal and for outputting a third signal representing that said arithmetic unit requires said second control information and said third control information queued in said control information buffer thereby executing an operation in accordance with said second control information, said third control information, and said memory operand.

Claim 13

A central processing unit as claimed in Claim 9, wherein said operand pre-fetch unit includes: (i) an operand reader for reading said memory operand; (ii) a first storage means for queueing said memory operand to send said memory operand to said arithmetic unit; and (iii) a first control unit for sending said first signal to said control information buffer when said memory operand is queued in said first storage means.

Claim 14

A central processing unit as claimed in Claim 9, wherein said control information buffer includes: (i) a second storage means for queueing said second control information and said third control information to send said second control information and said third control information to said arithmetic unit; (ii) a second control unit for outputting a fourth signal representing that said second control information and said third control information have been queued in said second storage means, and for receiving said third signal; (iii) a decoder for decoding said third control information thereby outputting a fifth signal representing that said third control information requires said memory operand; and (iv) a synchronizing circuit means responsive to said first, fourth, and fifth signals for outputting said second signal.

Claim 15

A central processing unit as claimed in Claim 9, wherein said arithmetic unit includes: (i) an arithmetic logic unit; (ii) a register bank having general purpose registers; and (iii) a third control unit for receiving said second signal and for outputting said third signal to said control information buffer.

Claim 16

A central processing unit comprising: (a) an instruction decoder for decoding an instruction to generate first control information, second control information, and third control information; (b) an operand address computation unit for computing an operand address in accordance with said first control information;. (c) an operand pre-fetch unit for fetching and queueing a memory operand in accordance with said operand address, and for outputting said memory operand and a first signal representing that said memory operand has been queued therein; (d) a control information buffer for queueing and outputting said second control information and said third control information, and for outputting a second signal representing that said second control informatoin and said third control information has been queued therein; and (e) an arithmetic unit for receiving said first and second signals and for outputting a third signal representing that said arithmetic unit requires said second control information and said third control information queued in said control information buffer thereby executing an operation in accordance with said second control information, said third control information, and said memory operand.

Claim 17

A central processing unit comprising: (a) an instruction decoder for decoding an instruction to generate first control information, second control information, and third control information; (b) an operand address computation unit for computing an operand address in accordance with said first control information;. (c) an operand pre-fetch unit for fetching and queueing a memory operand in accordance with said operand address, and for outputting said memory operand and a first signal representing that said memory operand has been queued therein; (d) a control information buffer for queueing and outputting said second control information and said third control information, and for outputting a second signal representing that said second control informatoin and said third control information has been queued therein; and (e) an arithmetic unit for receiving said first and second signals and for outputting a third signal representing that said arithmetic unit requires said second control information and said third control information queued in said control information buffer thereby executing an operation in accordance with said second control information, said third control information, and said memory operand.

Claim 18

A central processing unit as claimed in Claim 13, wherein said operand pre-fetch unit includes: (i) an operand reader for reading said memory operand; (ii) a first storage means for queueing said memory operand to send said memory operand to said arithmetic unit; and (iii) a first control unit for sending said first signal to said arithmetic unit when said memory operand is queued in said first storage means.

Claim 19

A central processing unit as claimed in Claim 13, wherein said control information buffer includes: (i) a second storage means for queueing said second control information and said third control information to send said second control information and said third control information to said arithmetic unit; and (ii) a second control unit for outputting said second signal, and for receiving said third signal.

Claim 20

A central processing unit as claimed in Claim 13, wherein said arithmetic unit includes: (i) an arithmetic logic unit; (ii) a register bank having general purpose registers; (iii) a decoder for decoding said third control information thereby outputting a fourth signal representing that said third control information requires said memory operand; (iv) a third control unit for outputting said third signal and a fifth signal representing that said second signal has been recieved, and for recieving said second signal and a sixth signal representing that said second and said third control information are valid; and (v) a synchronizing circuit means responsive to said first, fourth, and fifth signals for outputting said sixth signal.