Segment descriptor unit

Claim 2

A segment descriptor unit for performing translation operations on each word received by said unit, said unit comprising: a random access memory (RAM) having a plurality of storage locations, each location having a plurality of bit locations, a first group of bit locations of each of a first number of said plurality of storage locations storing information associated with a first type of translation operation and a second group of bit locations of said each of said first number of said storage locations storing information associated with a second type of translation operation; a content addressable memory (CAM) having a plurality of storage locations for storing information associated with a corresponding number of segment descriptor words to be translated and a plurality of outputs for generating hit signals indicating the results of comparing said each word to be translated with the information stored in said plurality of storage locations, said outputs being coupled to said RAM; and, microprogrammed control means coupled to said RAM and to said CAM, said control means generating first and second groups of signals for accessing the information contents of said first and second groups of bit locations respectively of one of said number of storage locations designated by said CAM hit signals for transfer to first and second devices respectively for performing operations for carrying out said first and second types of translation operations.

Claim 3

The segment descriptor unit of claim 1 wherein said unit further includes decoder means coupled to said RAM and to said microprogrammed control means, said decoder means being conditioned by a third group of signals from said microprogrammed control means to access a designated one of a second number of said plurality of locations used for storing working register information used during the performance of said first and second types of translation operations.

Claim 4

The segment descriptor unit of claim 1 wherein said microprogrammed control means includes a control store having a plurality of locations for storing a plurality of different types of microinstruction words, said control means in response to receiving said each word to be translated, reading out a first one of said different types of microinstruction words for generating said first group of signals for enabling said first device to perform operations for carrying out said first type of translation operation and said control means in response to said hit signals indicative of a miss condition reading out a second one of said different types of microinstruction words for generating said second group of signals for enabling said second device to perform operations for carrying out said second type of translation operation.

Claim 5

The segment descriptor unit of claim 3 wherein said first device corresponds to security checking circuits for verifying memory access based upon the state of said information stored in said first group of bit locations.

Claim 6

The segment descriptor unit of claim 3 wherein said second device is an adder for generating an address from said information stored in said second group of locations for accessing missing data required for completing the translation of said received word.

Claim 7

The segment descriptor unit of claim 2 wherein said unit further includes a register for storing each word required to be translated, said register being coupled to said decoder means, said decoder means being conditioned by signals from said register and signals from said second group of signals to access a designated one of a third number of said storage locations for generating an address for fetching information to be stored in said second group of bit locations of one of said first number of locations which caused said CAM to generate hit signals indicating a miss condition.

Claim 8

The segment descriptor unit of claim 1 wherein said unit is of VLSI chip construction and wherein said first group of bit locations and said second group of bit locations of said RAM are arranged in an alternating manner so that only that information necessary for performing said first and second translation operations by said first and second devices are accessible at different cycles of operation defined by said first and second groups of signals, said arrangement reducing the amount of chip space in conformance with the number of bits of information being operated on by said devices.

Claim 9

The segment descriptor unit of claim 7 wherein said first device includes a plurality of comparator sections and said second device includes a number of adder stages, a number of said adder stages being alternated with said comparator sections so as to minimize chip space requirements.

Claim 10

The segment descriptor unit of claim 7 wherein said RAM further includes a plurality of read/write amplifier circuits and a plurality of multiplexer circuits, each plurality corresponding in number to said first group of bit locations, said amplifier circuits and said multiplexer circuits being arranged in columns aligned with corresponding pairs of bit positions from said first and second groups of RAM bit locations, said multiplexer circuits being coupled to said microprogrammed control means, said multiplexer circuits in response to signals from said control means selecting which bit positions from said pairs of bit positions are to be connected to corresponding ones of said read/write amplifier circuits during a RAM read or write cycle of operation.

Claim 11

A segment descriptor unit for performing translation operations on each word received by said unit, said unit comprising: a random access memory (RAM) having a plurality of segment descriptor word (SDW) locations, each location being divided into a number of groups of bit positions for storing information pertaining to a corresponding number of different types of translation operations; a content addressable memory (CAM) having a plurality of storage locations for storing information associated with a corresponding number of segment descriptor words to be translated and a plurality of outputs for generating hit signals indicating the results of comparing said each word to be translated with the information stored in said CAM, said outputs being connected to said RAM; and, microprogrammed control means coupled to said RAM and to said CAM, said control means generating first and second pluralities of signals for accessing first and second ones of said number of groups respectively of one of said SDW locations designated by said CAM hit signals used for performing first and second types of translation operations.

Claim 12

A segment descriptor unit for performing translation operations on each word received by said unit, said unit comprising: a random access memory (RAM) having a plurality of segment descriptor word (SDW) locations, each location being divided into a number of groups of bit positions for storing information pertaining to a corresponding number of different types of translation operations; a content addressable memory (CAM) having a plurality of storage locations for storing information associated with a corresponding number of segment descriptor words to be translated and a plurality of outputs for generating hit signals indicating the results of comparing said each word to be translated with the information stored in said CAM, said outputs being connected to said RAM; and, microprogrammed control means coupled to said RAM and to said CAM, said control means generating first and second pluralities of signals for accessing first and second ones of said number of groups respectively of one of said SDW locations designated by said CAM hit signals used for performing first and second types of translation operations.

Claim 13

The segment descriptor unit of claim 10 wherein said unit further includes decoder means coupled to said RAM and to said microprogrammed control means, said decoder means being conditioned by a third group of signals from said microprogrammed control means to access a designated one of a second number of said plurality of locations used for storing working register information used during the performance of said first and second types of translation operations.

Claim 14

The segment descriptor unit of claim 10 wherein said microprogrammed control means includes a control store having a plurality of locations for storing a plurality of different types of microinstruction words, said control means in response to receiving said each word to be translated, reading out a first one of said different types of microinstruction words for generating said first group of signals for enabling a first device to perform operations for carrying out said first type of translation operation and said control means in response to said hit signals indicative of a miss condition reading out a second one of said different types of microinstruction words for generating said second group of signals for enabling a second device to perform operations for carrying out said second type of translation operation.

Claim 15

The segment descriptor unit of claim 12 wherein said first device corresponds to security checking circuits for verifying memory access based upon the state of said information stored in said first group of bit locations.

Claim 16

The segment descriptor unit of claim 12 wherein said second device is an adder for generating an address from said information stored in said second group of locations for accessing missing data required for completing the translation of said received word.

Claim 17

The segment descriptor unit of claim 11 wherein said unit further includes a virtual address register for storing each word required to be translated, said register being coupled to said decoder means, said decoder means being conditioned by signals from said register and signals from said second group of signals to access a designated one of a third number of said storage locations for generating an address for fetching information to be stored in said second group of bit locations of one of said first number of locations which caused said CAM to generate hit signals indicating a miss condition.

Claim 18

The segment descriptor unit of claim 10 wherein said unit is of VLSI chip construction and wherein said first group of bit locations and said second group of bit locations of said RAM are arranged in an alternating manner so that only that information necessary for performing said first and second translation operations by said first and second devices are accessible at different cycles of operation defined by said first and second groups of signals, said arrangement reducing the amount of chip space in conformance with the number of bits of information being operated on by said devices.

Claim 19

The segment descriptor unit of claim 16 wherein said first device includes a plurality of comparator sections and said second device includes a number of adder stages, a number of said adder stages being alternated with said comparator sections so as to minimize chip space requirements.

Claim 20

The segment descriptor unit of claim 16 wherein said RAM further includes a plurality of read/write amplifier circuits and a plurality of multiplexer circuits, each plurality corresponding in number to said first group of bit locations, said amplifier circuits and said multiplexer circuits being arranged in columns aligned with corresponding pairs of bit positions of said first and second groups of RAM bit locations, said multiplexer circuits being coupled to said microprogrammed control means, said multiplexer circuits in response to signals from said control means selecting which bit positions from said pairs of bit positions are to be connected to corresponding ones of said read/write amplifier circuits during a RAM read or write cycle of operation.

Claim 21

A VLSI segment descriptor unit for performing translation operations on each virtual address word received by said unit, said unit comprising: a random access memory (RAM) being equally divided into a pair of sections, each section having a plurality of bit cells arranged in rows and columns, and a plurality of word lines, each word line being connected to the bit cells of a different row and a plurality of bit lines, pairs of said bit lines being connected to the bit cells of a different column, first and second groups of bit cells of each of a first number of rows storing information pertaining to first and second different types of address translation operations; a content addressable memory (CAM) having an array for storing information associated with a corresponding number of segment descriptor words, said array containing a plurality of bit cells organized into a plurality of rows and columns and a plurality of hit lines, each of said bit cells within each different column being connected in common to a different one of said hit lines, said CAM being positioned between said pair of RAM sections so that a different one of said hit lines couples to a different one of said word lines of a first number of rows in each RAM section associated with the same row of bit cells and said CAM generating hit signals for indicating the results of comparing said each virtual address word with said information; and, microprogrammed control means coupled to said bit lines of each of said RAM sections, said control means generating signals for specifying said first and second different types of address translation operations, said signals selecting said bit lines of said first and second groups of bit cells of one of said first number of rows within said RAM sections designated by said hit signals applied to said CAM hit lines for read out of said information as a function of said type of address translation operation being performed.

Claim 22

A VLSI segment descriptor unit for performing translation operations on each virtual address word received by said unit, said unit comprising: a random access memory (RAM) being equally divided into a pair of sections, each section having a plurality of bit cells arranged in rows and columns, and a plurality of word lines, each word line being connected to the bit cells of a different row and a plurality of bit lines, pairs of said bit lines being connected to the bit cells of a different column, first and second groups of bit cells of each of a first number of rows storing information pertaining to first and second different types of address translation operations; a content addressable memory (CAM) having an array for storing information associated with a corresponding number of segment descriptor words, said array containing a plurality of bit cells organized into a plurality of rows and columns and a plurality of hit lines, each of said bit cells within each different column being connected in common to a different one of said hit lines, said CAM being positioned between said pair of RAM sections so that a different one of said hit lines couples to a different one of said word lines of a first number of rows in each RAM section associated with the same row of bit cells and said CAM generating hit signals for indicating the results of comparing said each virtual address word with said information; and, microprogrammed control means coupled to said bit lines of each of said RAM sections, said control means generating signals for specifying said first and second different types of address translation operations, said signals selecting said bit lines of said first and second groups of bit cells of one of said first number of rows within said RAM sections designated by said hit signals applied to said CAM hit lines for read out of said information as a function of said type of address translation operation being performed.

Claim 23

The segment descriptor unit of claim 19 wherein said unit further includes: decoder means coupled to said microprogrammed control means and to a second number of said word lines of a second number of rows in said each RAM section associated with the same row of bit cells, said decoder means being conditioned by signals from said control means to access said first and second groups of bit cells of one of said second number of rows within said each RAM section for storing information used during the performance of said first and second types of translation operations.

Claim 24

The segment descriptor unit of claim 20 wherein said information stored in said first group of bit cells of said second number of rows includes addresses for fetching segment descriptor information indicated by said hit signals as being not stored in said CAM.

Claim 25

The segment descriptor unit of claim 20 wherein said second group of bit cells of said second number of rows are available as working register storage usable during said first and second translation operations.

Claim 26

The segment descriptor unit of claim 19 wherein said unit further includes first and second devices coupled to said RAM sections, said microprogrammed control means including a control store having a plurality of locations for storing a plurality of different types of microinstruction words, said control means in response to receiving said each word to be translated, reading out a first one of said different types of microinstruction words for generating first ones of signals for enabling said first device to perform operations for carrying out said first type of translation operation and said control means in response to said hit signals indicative of a miss condition reading out a second one of said different types of microinstruction words for generating second ones of said signals for enabling said second device to perform operations for carrying out said second type of translation operation.

Claim 27

The segment descriptor unit of claim 23 wherein said first device corresponds to security checking circuits for verifying memory access based upon the state of said information stored in said first group of bit cells.

Claim 28

The segment descriptor unit of claim 23 wherein said second device is an adder for generating an address from said information stored in said second group of bit cells for accessing missing data required for completing the translation of said virtual address word.

Claim 29

The segment descriptor unit of claim 23 wherein said first device includes a plurality of comparator sections and said second device includes a number of adder stages, a number of said adder stages being alternated with said comparator sections so as to minimize chip space requirements.

Claim 30

The segment descriptor unit of claim 19 wherein each of said RAM sections further includes a plurality of read/write amplifier circuits and a plurality of multiplexer circuits, each plurality corresponding in number to said first group of bit locations, said amplifier circuits and said multiplexer circuits being arranged in columns aligned with corresponding pairs of columns of said first and second groups of RAM bit cells, said multiplexer circuits being coupled in series with said multiplexer circuits in response to signals from said control means selecting which column of said pairs of columns of bit cells are to be connected to corresponding ones of said read/write amplifier circuits during a RAM read or write cycle of operation.