Static semiconductor memory device having improved pull-up operation for bit lines

Claim 2

A semiconductor memory device comprising: static memory cells (C 00 , C 01 , ...), provided at each intersection between a plurality of word lines (WL 0 , WL 1 , ...) and a plurality of bit line pairs (BL 0 , BL 0 , ...) ; suppressing means provided at each of said bit line pairs, for suppressing the reduction of the potential of the lower level bit line of each bit line pair; 'word line selection means (RD) for selecting one of the word lines; bit line pair selection means for selection one bit line pair and prohibiting the suppressing operation of the reduction of the potential of the lower level bit line of that pair by the suppressing means.

Claim 3

A device according to claim 1, wherein the suppressing means includes load transistors (Q L0 , Q L0 ', ..., Q L,n-1 , Q L,n-1 '), connected between the bit line pairs and a power suply, the load transistors being turned ON when the corresponding bit line pairs are not selected by the bit line pair selection means.

Claim 4

A device according to claim 1 or 2, wherein the suppressing means includes: a connection line (L) provided at the bit line pairs; and, a plurality of transistors (Q L0 ", Q L0 "', ..., Q L,n-1 ", Q L,n-1 "'), connected between the bit line pairs and the connection line, the transistors being turned ON when the corresponding bit line pairs are not selected by the bit line pair selection means.

Claim 5

A device according to claim 1, 2 or 3, wherein the suppressing means includes bit line short-circuiting means (Q SO' Q S1' ...), provided for each of the bit line pairs, for suppressing the reduction of the potential of the lower level bit lines of the bit line pairs, the bit line short-circuiting means being turned ON when the corresponding bit line pairs are not selected by the bit line selection means.

Claim 6

A semiconductor memory device comprising: static memory cells (C 00 , C 01 , ...), provided at each intersection between a plurality of word lines (WL 0 , WL 1 , ...) and a plurality of bit line pairs BL 0 , BL O , ...) ; a plurality of pull-up means (Q L0 , Q L0 ', ...) provided at each of said bit line pairs; a connection line (L), provided at said bit line pairs, for suppressing the reduction of the potential of the lower level bit line of said bit line pairs; word line selection means (RD) for selecting said word lines; bit line pair section means for selecting one of said bit line pairs and connecting bit line pairs other than the selected bit line pairs to said connection line.

Claim 7

A semiconductor memory device comprising: static memory cells (C 00 , C 01 , ...), provided at each intersection between a plurality of word lines (WL 0 , WL 1 , ...) and a plurality of bit line pairs BL 0 , BL O , ...) ; a plurality of pull-up means (Q L0 , Q L0 ', ...) provided at each of said bit line pairs; a connection line (L), provided at said bit line pairs, for suppressing the reduction of the potential of the lower level bit line of said bit line pairs; word line selection means (RD) for selecting said word lines; bit line pair section means for selecting one of said bit line pairs and connecting bit line pairs other than the selected bit line pairs to said connection line.

Claim 8

A device according to claim 5, further comprising bit line short-circuiting means (Q SO' Q S1 , ...), provided for each of said bit line pairs, for suppressing the reduction of the potential of the lower level bit line of said bit line pairs, said bit line pair selection means (Q S0 , Q S1 , ...) short-circuiting bit line pairs other than the selected bit line pairs.

Claim 9

A semiconductor memory device comprising: static memory cells (C 00 , C 01 , ...), provided at each intersection between a plurality of word lines (WL O , WL 1 , ...) and a plurality of bit line pairs (BL 0 , BL 0 , ...) ; a plurality of pull-u p means (Q L0 , Q L0 ', ...), provided at each of said bit line pairs; bit line short-circuiting means (Q S0 , Q S1 , ...), provided for each of said bit line pairs, for suppressing the reduction of the lower level bit lines of said bit line pairs; word line selection means (RD) for selecting one of said word lines; /bit line pair selection means for selecting one of said bit line pairs and short-circuiting bit line pairs other than the selected bit line pairs.

Claim 10

A semiconductor memory device comprising: static memory cells (C 00 , C 01 , ...), provided at each intersection between a plurality of word lines (WL O , WL 1 , ...) and a plurality of bit line pairs (BL 0 , BL 0 , ...) ; a plurality of pull-u p means (Q L0 , Q L0 ', ...), provided at each of said bit line pairs; bit line short-circuiting means (Q S0 , Q S1 , ...), provided for each of said bit line pairs, for suppressing the reduction of the lower level bit lines of said bit line pairs; word line selection means (RD) for selecting one of said word lines; /bit line pair selection means for selecting one of said bit line pairs and short-circuiting bit line pairs other than the selected bit line pairs.