EP0269980A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data processor for parallelly executing conflicting instructions

Assignee: Hitachi Ltd

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Filing: 1987-11-24

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Granted: —

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Expires: 2007-11-24

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Abstract

Abstract A data processor includes a storage (50, 51, 52) and a general register group (70) for storing an operand; an operand hold unit (60) for storing operands read from the storage for a plurality of instructions and providing at least two operands; an operand select unit (80, 85) connected to the operand hold unit and the general register group for selecting either one of the operands for a preceding instruction and a succeeding instruction; at least one arithmetic or logical operation unit (80, 81) connected to the operand select unit; a decode unit (20, 21) for sequentially decoding instructions to be executed and generating instruction decode informations; an instruction hold unit (30) for storing a plurality of instruction decode informations generated by the decode unit and providing at least two instruction decode informations; an instruction detection unit (90, 920) for detecting that a succeeding instruction writes a read-out operand into the general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by the instruction hold unit; a conflict detection unit (90, 940) for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit (90, 913) for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.

Inventors

👤 Eiki Kamada
👤 Yooichi Shintani
👤 Kazunori Kuriyama
👤 Tohru Shonai
👤 Kiyoshi Inoue

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-10-28 16:52

CPC Classifications

G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836

Claims Analysis

Total Claims: 5

Claim 1

Independent Claim 212 words

A data processor for parallelly executing a plurality of instructions, comprising: (a) a storage (52, 50, 51) for storing operands; (b) a group of registers (70) each for storing an operand; (c) operand means (60) for storing operands of a plurality of instructions, said operands being read from said storage thereto; (d) means (20, 21, 30) for decoding instructions to be executed and providing decode information of at least two instructions to be subjected to an arithmetic or logical operation; (e) instruction detection means (90) for detecting, based on said instruction decode information of said at least two instructions supplied from said decode means, that a preceding instruction among said at least two instructions requests reading of an operand from said storage or from said register group and writing of said operand into a register of said register group without performing an arithmetic or logical operation of said operand, and that a succeeding instruction among said at least two instructions requests reading of said operand in said register and performing of an arithmetic or logical operation thereon; and (f) execution means (80, 81, 95, 97, 87, 89) responsive to the detection by said instruction detection means for concurrently performing arithmetic or logical operation stages of said preceding instruction and said succeeding instructions.

Claim 2

Dependent Claim 212 words

Claim 3

Dependent Claim 85 words

A data processor according to claim 1 wherein said execution means comprises (f1) at least one operation means (81, 82) for performing an arithmetic or logical operation; (f2) means (87, 89) for supplying the operand requested by said preceding instruction from said operand means or from said register group to said at least one operation means; and (f3) means (95, 97) for causing said at least one operation means to perform the arithmetic or logical operation requested by said succeeding instruction on said supplied operand.

Claim 4

Dependent Claim 65 words

A data processor according to claim 2, wherein said execution means includes means for allowing writing of an operation result of said succeeding instruction outputted from said at least one operation means without writing said supplied operand of the preceding instruction into said register of said register group, when said succeeding instruction requests writing of said operation result into said register of said register group.

Claim 5

Dependent Claim 65 words

A data processor according to claim 2, wherein said execution means includes means for allowing writing of said supplied operand for the preceding instruction and allowing writing of an operation result of said succeeding instruction outputted from said at least one operation means, when said succeeding instruction requests writing of said operation result into a register different from said register of said general register group.

References Cited (Backward Citations)

JPS5646170A Cited

JPS58176751A Cited

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