Logic circuit for expansion of monochrome display patterns to color form and video controller comprising such logic circuit

Claim 2

A logic circuit for use in a color imaging system, for expanding a monochrome image having one bit per picture element to a color image having multiple bits per picture element, and for integration of that expanded image into an existing image in a memory, comprising: an expander circuit including: a) a source latch for storing a part of said monochrome image; b) extension latch means for defining an extension factor between one and an upper boundary that is greater than one; c) source tracking means for determining successive currently-operating parts of said source latch, and signal a need to reload said source latch from memory; d) expansion logic having inputs fed by outputs of said source latch, said extension latch means, and said source tracking means; and having as its outputs a signal representing one of an expanded and a non-expanded version of the contents of said source latch, wherein the number of consecutive bits indicated by the extension latch means correspond to one bit in the source latch;

Claim 3

alignment means which shift the output of said expansion logic in said expander circuit, to correspond to the positioning of destination words in said memory; clipping means which preserve parts of destination words in said memory, which are outside of said expanded image; a pattern generator circuit comprising: a) a foreground register programmable with picture element value(s) which are to be substituted for ONES in said monochrome image; b) a background register programmable with picture element value(s) that can optionally be substituted for ZEROS in said monochrome image; c) a single-bit register programmable to alternately control picture elements corresponding to zeroes in said monochrome image 1) to be left unchanged, or 2) to be changed to the contents of said background register; d) a destination latch, in which the contents of destination words in memory can be temporarily stored; e) multiplexing logic which selects among the contents of said foreground register, said background register, and said destination latch, under control of the output of said single-bit register, said alignment means, and said clipping means; having as its output new contents for the current destination word; and control means which sequence the reading of memory data and its storage in said source and destination latches, and the writing of said new contents to memory.

Claim 4

alignment means which shift the output of said expansion logic in said expander circuit, to correspond to the positioning of destination words in said memory; clipping means which preserve parts of destination words in said memory, which are outside of said expanded image; a pattern generator circuit comprising: a) a foreground register programmable with picture element value(s) which are to be substituted for ONES in said monochrome image; b) a background register programmable with picture element value(s) that can optionally be substituted for ZEROS in said monochrome image; c) a single-bit register programmable to alternately control picture elements corresponding to zeroes in said monochrome image 1) to be left unchanged, or 2) to be changed to the contents of said background register; d) a destination latch, in which the contents of destination words in memory can be temporarily stored; e) multiplexing logic which selects among the contents of said foreground register, said background register, and said destination latch, under control of the output of said single-bit register, said alignment means, and said clipping means; having as its output new contents for the current destination word; and control means which sequence the reading of memory data and its storage in said source and destination latches, and the writing of said new contents to memory.

Claim 5

The logic circuit as claimed in Claim 1, wherein said bits per pixel means are programmable for 1, 2, 4 or 8 bits/pixel.

Claim 6

A logic circuit as claimed in Claims 1 or 2, wherein said source tracking means comprises a counter capable of counting from zero through the number of bits per pixel minus 1, and a multiplexer having as its data inputs the outputs of said counter and having as its control inputs the outputs of said extension latch means; said multiplexer having as its output a signal indicating whether said source latch needs to be reloaded.

Claim 7

A logic circuit as claimed in Claims 1, 2 or 3, wherein said expansion logic is a logic array (PLA) structure.

Claim 8

In a video controller which receives bit mapped source pattern data from a display memory and converts said data into output signals for controlling a raster scan video display, the improvement comprising: means which store color data which is associated with particular monochrome shape/image/character patterns in the display memory and means which expand the data received from said display memory to selectively add color information to representations of said monochrome patterns in said output signal as claimed in any of Claims 1 through 4.

Claim 9

A logic circuit for expanding a monochrome image of a raster scan display to a color image while minimizing display memory storage requirements for use in a raster scan video contoller of a computer display system, comprising: a control unit to control operations of said circuit; an expander circuit comprising: a programmable bits per pixel register defining the number of bits per pixel for a colored/expander image; a counter to control the output sequence of expanded, source patterns; a source pattern latch which receives sequentially monochrome source patterns from display memory having one bit per pixel and defining shapes to be expanded and displayed; a programmed logic array having as inputs the contents of said source pattern latch, said bits per pixel register, and said counter; the output of the PLA being a sequence of expanded source patterns; a multiplexer connected to said counter and said bits per pixel register to produce a zero output indicating the completion of the expansion of one source pattern from said source pattern latch and a signal to said control unit to fetch the next source pattern, said signal being asserted when the output of said counter equals the value in said bits per pixel register; a pattern generator having: a foreground color latch programmable with a color code selected for a foreground iamge; a background color latch programmable with a color code selected for the background of a displayed image; a destination latch to receive sequentially destination patterns in display memory having one bit per pixel indicating which pixels are part of an image to be displayed; a write/overlay register programmable to indicate whether the background of an image to be displayed should be filled; a multiplexer to select between data in said destination latch and said background color latch under the control of said write/overlay register; means under control of said expanded source pattern output from said expander to select between data in said foreground latch and from said multiplexer, said latter selected data being data for the colored and/or expanded image for said display.

Claim 10

A logic circuit for expanding a monochrome image of a raster scan display to a color image while minimizing display memory storage requirements for use in a raster scan video contoller of a computer display system, comprising: a control unit to control operations of said circuit; an expander circuit comprising: a programmable bits per pixel register defining the number of bits per pixel for a colored/expander image; a counter to control the output sequence of expanded, source patterns; a source pattern latch which receives sequentially monochrome source patterns from display memory having one bit per pixel and defining shapes to be expanded and displayed; a programmed logic array having as inputs the contents of said source pattern latch, said bits per pixel register, and said counter; the output of the PLA being a sequence of expanded source patterns; a multiplexer connected to said counter and said bits per pixel register to produce a zero output indicating the completion of the expansion of one source pattern from said source pattern latch and a signal to said control unit to fetch the next source pattern, said signal being asserted when the output of said counter equals the value in said bits per pixel register; a pattern generator having: a foreground color latch programmable with a color code selected for a foreground iamge; a background color latch programmable with a color code selected for the background of a displayed image; a destination latch to receive sequentially destination patterns in display memory having one bit per pixel indicating which pixels are part of an image to be displayed; a write/overlay register programmable to indicate whether the background of an image to be displayed should be filled; a multiplexer to select between data in said destination latch and said background color latch under the control of said write/overlay register; means under control of said expanded source pattern output from said expander to select between data in said foreground latch and from said multiplexer, said latter selected data being data for the colored and/or expanded image for said display.

Claim 11

The logic circuit of Claim 6 wherein said bits per pixel register may be programmed for one, two, four or eight bits per pixel.

Claim 12

The logic circuit of Claim 6 wherein a zero in a source pattern is expanded to a color code programmed into said background latch.

Claim 13

The logic circuit of Claim 6 wherein a zero in a source pattern is left unchanged.

Claim 14

The logic circuit of Claim 6 wherein said source pattern is a character font.